Rodrigo Vivi <rodrigo.v...@intel.com> writes:

> "Clock gating bug in GWL may not clear barrier state when an EOT
> is received, causing a hang the next time that barrier is used."
>
> HSDES: 2201832410
>

A bit late here but do we have a preference of going like
the above or,

References: HSDES#2201832410

?
-Mika


> Cc: Rafael Antognolli <rafael.antogno...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4787d9bf58b9..e6a8c0ee7df1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3965,6 +3965,9 @@ enum {
>  #define  SARBUNIT_CLKGATE_DIS                (1 << 5)
>  #define  RCCUNIT_CLKGATE_DIS         (1 << 7)
>  
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE  _MMIO(0x9524)
> +#define  GWUNIT_CLKGATE_DIS          (1 << 16)
> +
>  #define UNSLICE_UNIT_LEVEL_CLKGATE   _MMIO(0x9434)
>  #define  VFUNIT_CLKGATE_DIS          (1 << 20)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6cab20ce167a..b8da4dcdd584 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>               val |= SARBUNIT_CLKGATE_DIS;
>       I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>  
> +     /* Wa_2201832410:cnl */
> +     val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> +     val |= GWUNIT_CLKGATE_DIS;
> +     I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> +
>       /* WaDisableVFclkgate:cnl */
>       /* WaVFUnitClockGatingDisable:cnl */
>       val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> -- 
> 2.13.6
>
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