Read ordering on cpu can be out of order and speculative.
In addition, the access to the hardware status page is snooped.
This raises a concern that we might use the HWSP in an unexpected
way as we may load the head of a cbs entry before we access the tail.
Concerns like that the coherency protocol is tied somehow to the
tail read snoop.

To enforce that we really do read the tail before we fetch
the csb entry pointed by head, insert a read memory barrier after we
have read the tail.

This fixes, or masks due to added latency, context status
buffer incoherence on cnl, where we see an old context status
entry still on that a csb slot.

Cc: Chris Wilson <>
Cc: Rafael Antognolli <>
Cc: Vivi, Rodrigo <>
Signed-off-by: Mika Kuoppala <>
 drivers/gpu/drm/i915/intel_lrc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c7c85134a84a..5378391e1e71 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -969,6 +969,8 @@ static void execlists_submission_tasklet(unsigned long data)
                        head = execlists->csb_head;
                        tail = READ_ONCE(buf[write_idx]);
+                       /* Enforce ordering of reads into the HWSP */
+                       rmb();
                GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",

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