On Sun, Nov 11, 2012 at 09:34:06AM -0800, Ben Widawsky wrote: > On Sun, 11 Nov 2012 09:34:45 +0000 > Chris Wilson <[email protected]> wrote: > > > ...rather than kilo-PTE. > > > > Signed-off-by: Chris Wilson <[email protected]> > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index e7515e8..938710a 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -708,7 +708,7 @@ int i915_gem_gtt_init(struct drm_device *dev) > > } > > > > /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in > > a linear fashion. */ > > - DRM_INFO("Memory Usable by graphics device = %dK\n", > > dev_priv->mm.gtt->gtt_total_entries >> 10); > > + DRM_INFO("Memory Usable by graphics device = %dM\n", > > dev_priv->mm.gtt->gtt_total_entries >> 8); > > DRM_DEBUG_DRIVER("GMADR size = %dM\n", > > dev_priv->mm.gtt->gtt_mappable_entries >> 8); > > DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", > > dev_priv->mm.gtt->stolen_size >> 20); > > > > Shouldn't it be >> 18 though, not >> 8?
Each pte entry stands for a 4k page, so entries is already size >> 12, so we only need to shift by 8 to get M. Patch merged to dinq. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
