Disable GWL clock gating to prevent an issue that might
cause hangs.
v2: Rebased on top of the WA refactoring
v3: Wa_2201832410 officially merged with Wa_1406680159
v4: Added References (Mika)
v5:
- Rebased
- C, not lisp (Chris)
- Add reference where WA is better explained (Rodrigo)
- Add reference to WA that got merged with this
References: HSDES#1406681710
References: HSDES#1406680159
References: HSDES#2201832410
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 469a83d..a3fa01a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS);
+
+ /* Wa_1406680159:icl */
+ I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+ I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+ GWUNIT_CLKGATE_DIS);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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