We'll use those helpers in the following commits. It's a good thing to
have them around as they need to apply a particular workaround on
Skylake.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 34 +++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e754e9d112a5..6fe0d668c023 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2151,6 +2151,40 @@ static void gen8_emit_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
}
static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
+u32 gen8_lri_pipe_control_len(struct drm_i915_private *dev_priv)
+{
+ return IS_SKYLAKE(dev_priv) ? (7) : 5;
+}
+
+u32 *gen8_emit_lri_pipe_control(struct drm_i915_private *dev_priv,
+ u32 *cs, u32 flags, u32 offset,
+ u32 value)
+{
+ /*
+ * Project: SKL
+ *
+ * "PIPECONTROL command with "Command Streamer Stall Enable" must be
+ * programmed prior to programming a PIPECONTROL command with LRI
+ * Post Sync Operation in GPGPU mode of operation (i.e when
+ * PIPELINE_SELECT command is set to GPGPU mode of operation)."
+ *
+ * Since the mode of operation is selected from userspace, we apply
+ * this workaround all the time one SKL.
+ */
+ if (IS_SKYLAKE(dev_priv)) {
+ *cs++ = GFX_OP_PIPE_CONTROL(2);
+ *cs++ = PIPE_CONTROL_CS_STALL;
+ }
+
+ *cs++ = GFX_OP_PIPE_CONTROL(5);
+ *cs++ = PIPE_CONTROL_MMIO_WRITE | flags;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
+}
+
static int gen8_init_rcs_context(struct i915_request *rq)
{
int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 010750e8ee44..aa643a1d69db 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -1042,6 +1042,11 @@ gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)
return cs;
}
+u32 gen8_lri_pipe_control_len(struct drm_i915_private *dev_priv);
+u32 *gen8_emit_lri_pipe_control(struct drm_i915_private *dev_priv,
+ u32 *cs, u32 flags, u32 offset,
+ u32 value);
+
bool intel_engine_is_idle(struct intel_engine_cs *engine);
bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
--
2.17.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
