Use the correct engine class shift value while storing the ctx hw id.
Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
ctx_id read with GuC & ICL").
Apologies for not spotting this in the original review, the
specific_ctx_id_mask is correct, only the specific_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry <[email protected]>
Cc: Lionel Landwerlin <[email protected]>
Cc: Chris Wilson <[email protected]>
---
drivers/gpu/drm/i915/i915_perf.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 36b6d64d6018..d049fde46dec 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1287,12 +1287,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
break;
case 11: {
- struct intel_engine_cs *engine = i915->engine[RCS];
-
- i915->perf.oa.specific_ctx_id =
- stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
- engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
- engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
+ i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc);
i915->perf.oa.specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
(GEN11_SW_CTX_ID_SHIFT - 32) |
((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) <<
(GEN11_ENGINE_INSTANCE_SHIFT - 32) |
--
2.17.1
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