On 11/29/12 8:29 AM, Paulo Zanoni wrote:
From: Paulo Zanoni <[email protected]>
The previous code was making the bps value 5% higher than what the
spec says, which was enough to make certain VGA modes require 3 lanes
instead of 2, which makes us reject these modes on Haswell since it
only has 2 FDI lanes. For previous gens this was not much of a
problem, since they had 4 lanes, and requiring more lanes than the
needed is ok, as long as you have all the lanes.
Notice that this might improve the case where we use pipes B and C on
Ivy Bridge since both pipes only have 4 lanes to share (see
ironlake_check_fdi_lanes).
Fine with me. I'm not entirely sure the SS check I had there was
necessary; I do remember the docs saying to account for it, but I'm not
sure the check we had there was correct.
Reviewed-by: Adam Jackson <[email protected]>
- ajax
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