On Fri, 2018-06-15 at 16:03 -0700, José Roberto de Souza wrote: > > Sink can be configured to calculate the CRC over the static frame and > compare with the CRC calculated and transmited in the VSC SDP by > source, if there is a mismatch sink will do a short pulse in HPD > and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS. > > Spec: 7723 > > v4: > patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout' > to avoid touch in 2 patches EDP_PSR_DEBUG. > > v3: > disabling PSR instead of exiting on error > > Cc: Dhinakaran Pandiyan <[email protected]> > Cc: Rodrigo Vivi <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_psr.c | 7 ++++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index b8c0ebd50889..11726ef0c0b6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4038,6 +4038,7 @@ enum { > #define EDP_PSR_SKIP_AUX_EXIT (1<<12) > #define EDP_PSR_TP1_TP2_SEL (0<<11) > #define EDP_PSR_TP1_TP3_SEL (1<<11) > +#define EDP_PSR_CRC_ENABLE (1<<10) /* BDW+ > */ > #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) > #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) > #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index be4611963044..3b045156b2c0 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -360,6 +360,8 @@ static void hsw_psr_enable_sink(struct intel_dp > *intel_dp) > > if (dev_priv->psr.link_standby) > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; > + if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) > + dpcd_val |= DP_PSR_CRC_VERIFICATION; > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > @@ -415,6 +417,9 @@ static void hsw_activate_psr1(struct intel_dp > *intel_dp) > else > val |= EDP_PSR_TP1_TP2_SEL; > > + if (INTEL_GEN(dev_priv) >= 8) > + val |= EDP_PSR_CRC_ENABLE; > + > val |= I915_READ(EDP_PSR_CTL) & > EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; > I915_WRITE(EDP_PSR_CTL, val); > } > @@ -1051,7 +1056,7 @@ void intel_psr_short_pulse(struct intel_dp > *intel_dp) This comment change doesn't look like it belongs here.
I also think you could have left the check for LINK_CRC_ERROR in this this patch. Anyway, the series looks good overall Reviewed-by: Dhinakaran Pandiyan <[email protected]> for the series. When resending this patch, please consider removing "bdw+" from the title as "drm/i915/psr" is a sufficient and consistent prefix. > > /* clear status register */ > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, > val); > > - /* TODO: handle other PSR/PSR2 errors */ > + /* TODO: handle PSR2 errors */ > exit: > mutex_unlock(&psr->lock); > } _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
