On Thu, Jul 05, 2018 at 05:52:16PM +0100, Chris Wilson wrote: > Quoting Ville Syrjala (2018-07-05 17:43:56) > > From: Ville Syrjälä <[email protected]> > > > > Make sure our hpd pin count doesn't exceed the bitmasks we use > > for tracking pending hotplugs. Not ever close to the limit yet, > > but no harm in making sure either. > > > > Signed-off-by: Ville Syrjälä <[email protected]> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > > b/drivers/gpu/drm/i915/i915_irq.c > > index bb7c754979f8..c107e0837026 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1713,6 +1713,8 @@ static void intel_get_hpd_pins(struct > > drm_i915_private *dev_priv, > > { > > enum hpd_pin pin; > > > > + BUILD_BUG_ON(HPD_NUM_PINS > 32); > > sizeof(*pin_mask) * CHAR_BIT ?
For a slightly more pleasing appearance I suppose we might want to steal BITS_PER_TYPE() from include/linux/net_dim.h. A quick grep didn't seem to reveal anything similar in a more general location. > > Just looking for some explanation as where the limit comes from. Now > obviously u32, but why was u32 chosen? Had the right kind of smell perhaps? -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
