> -----Original Message----- > From: Chris Wilson <[email protected]> > Sent: Thursday, July 12, 2018 11:53 AM > To: [email protected] > Cc: Chris Wilson <[email protected]>; Zhenyu Wang > <[email protected]>; Bloomfield, Jon <[email protected]>; > Joonas Lahtinen <[email protected]>; Matthew Auld > <[email protected]> > Subject: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT > > GVT is not propagating the PTE bits, and is always setting the > read-write bit, thus breaking read-only support. > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Zhenyu Wang <[email protected]> > Cc: Jon Bloomfield <[email protected]> > Cc: Joonas Lahtinen <[email protected]> > Cc: Matthew Auld <[email protected]> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 6c0b438afe46..8e70a45b8a90 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1662,8 +1662,12 @@ static struct i915_hw_ppgtt > *gen8_ppgtt_create(struct drm_i915_private *i915) > 1ULL << 48 : > 1ULL << 32; > > - /* From bdw, there is support for read-only pages in the PPGTT */ > - ppgtt->vm.has_read_only = true; > + /* > + * From bdw, there is support for read-only pages in the PPGTT. > + * > + * XXX GVT is not setting honouring the PTE bits. > + */ > + ppgtt->vm.has_read_only = !intel_vgpu_active(i915); > > i915_address_space_init(&ppgtt->vm, i915); > > -- > 2.18.0
Is there a blocker that prevents gvt respecting this bit? I can't think of an obvious reason why it would be a bad thing to support. _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
