> -----Original Message----- > From: Ville Syrjälä [mailto:[email protected]] > Sent: Thursday, July 19, 2018 9:53 PM > To: Chauhan, Madhav <[email protected]> > Cc: [email protected]; Nikula, Jani <[email protected]>; > Zanoni, Paulo R <[email protected]>; Vivi, Rodrigo > <[email protected]> > Subject: Re: [Intel-gfx] [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO > of DSI transcoder registers > > On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote: > > This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing DSI > > transcoder registers. > > > > Credits-to: Jani N > > > > Cc: Jani Nikula <[email protected]> > > Signed-off-by: Madhav Chauhan <[email protected]> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 1d13ba9..62bc76e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9576,6 +9576,11 @@ enum skl_power_gate { > > #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* > ports A and C only */ > > #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) > > > > +/* gen11 DSI */ > > +#define _DSI_TRANS(tc, dsi0, dsi1) (((tc) == TRANSCODER_DSI_0) ? \ > > + (dsi0) : (dsi1)) > > _PIPE() etc. should result in slughtly better code IIRC.
Are you suggesting to use following, please clarify?? #define _DSI_TRANS(tc, dsi0, dsi1) _PIPE(tc, dsi0, dsi1) Regards, Madhav > > > +#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO(_DSI_TRANS(tc, dsi0, dsi1)) > > + > > #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) > > #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF > > #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > [email protected] > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
