Currently tests modify i915.enable_psr and then do a modeset cycle to change PSR. We can write a value to i915_edp_psr_status to force a certain value without a modeset.
To retain compatibility with older userspace, we also still allow the override through the module parameter, and add some tracking to check whether a debugfs mode is specified. Changes since v1: - Rename dev_priv->psr.enabled to .dp, and .hw_configured to .enabled. - Fix i915_psr_debugfs_mode to match the writes to debugfs. - Rename __i915_edp_psr_write to intel_psr_set_debugfs_mode, simplify it and move it to intel_psr.c. This keeps all internals in intel_psr.c - Perform an interruptible wait for hw completion outside of the psr lock, instead of being forced to trywait and return -EBUSY. Changes since v2: - Rebase on top of intel_psr changes. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Dhinakaran Pandiyan <[email protected]> --- drivers/gpu/drm/i915/i915_debugfs.c | 75 ++++++++++++-- drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/intel_drv.h | 3 + drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++---- 4 files changed, 214 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 59dc0610ea44..b2904bb2be49 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2689,14 +2689,11 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m) static int i915_edp_psr_status(struct seq_file *m, void *data) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_i915_private *dev_priv = m->private; u32 psrperf = 0; bool enabled = false; bool sink_support; - if (!HAS_PSR(dev_priv)) - return -ENODEV; - sink_support = dev_priv->psr.sink_support; seq_printf(m, "Sink_Support: %s\n", yesno(sink_support)); if (!sink_support) @@ -2705,7 +2702,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); mutex_lock(&dev_priv->psr.lock); - seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); + seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled)); seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", dev_priv->psr.busy_frontbuffer_bits); @@ -2776,6 +2773,72 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, i915_edp_psr_debug_get, i915_edp_psr_debug_set, "%llu\n"); +static ssize_t i915_edp_psr_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + struct drm_modeset_acquire_ctx ctx; + int ret, val; + + if (!dev_priv->psr.sink_support) + return -ENODEV; + + ret = kstrtoint_from_user(ubuf, len, 10, &val); + if (ret < 0) { + bool enable; + ret = kstrtobool_from_user(ubuf, len, &enable); + + if (ret < 0) + return ret; + + val = enable; + } + + if (val != PSR_DEBUGFS_MODE_DEFAULT && + val != PSR_DEBUGFS_MODE_DISABLED && + val != PSR_DEBUGFS_MODE_ENABLED) + return -EINVAL; + + intel_runtime_pm_get(dev_priv); + + drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); + +retry: + ret = intel_psr_set_debugfs_mode(dev_priv, &ctx, val); + if (ret == -EBUSY) { + ret = drm_modeset_backoff(&ctx); + if (!ret) + goto retry; + } + + drm_modeset_drop_locks(&ctx); + drm_modeset_acquire_fini(&ctx); + + intel_runtime_pm_put(dev_priv); + + return ret ?: len; +} + +static int i915_edp_psr_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + if (!HAS_PSR(dev_priv)) + return -ENODEV; + + return single_open(file, i915_edp_psr_status, dev_priv); +} + +static const struct file_operations i915_edp_psr_ops = { + .owner = THIS_MODULE, + .open = i915_edp_psr_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_edp_psr_write +}; + static int i915_energy_uJ(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4720,7 +4783,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_swizzle_info", i915_swizzle_info, 0}, {"i915_ppgtt_info", i915_ppgtt_info, 0}, {"i915_llc", i915_llc, 0}, - {"i915_edp_psr_status", i915_edp_psr_status, 0}, {"i915_energy_uJ", i915_energy_uJ, 0}, {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, {"i915_power_domain_info", i915_power_domain_info, 0}, @@ -4744,6 +4806,7 @@ static const struct i915_debugfs_files { const struct file_operations *fops; } i915_debugfs_files[] = { {"i915_wedged", &i915_wedged_fops}, + {"i915_edp_psr_status", &i915_edp_psr_ops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, {"i915_ring_test_irq", &i915_ring_test_irq_fops}, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f49f9988dfa..d8583770e8a6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -612,7 +612,8 @@ struct i915_drrs { struct i915_psr { struct mutex lock; bool sink_support; - struct intel_dp *enabled; + bool enabled; + struct intel_dp *dp; bool active; struct work_struct work; unsigned busy_frontbuffer_bits; @@ -625,6 +626,12 @@ struct i915_psr { bool debug; ktime_t last_entry_attempt; ktime_t last_exit; + + enum i915_psr_debugfs_mode { + PSR_DEBUGFS_MODE_DEFAULT = -1, + PSR_DEBUGFS_MODE_DISABLED, + PSR_DEBUGFS_MODE_ENABLED + } debugfs_mode; }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c275f91244a6..751ed257fbba 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1926,6 +1926,9 @@ void intel_psr_enable(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state); +int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, + struct drm_modeset_acquire_ctx *ctx, + enum i915_psr_debugfs_mode mode); void intel_psr_invalidate(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits, enum fb_op_origin origin); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 4bd5768731ee..97424ae769f3 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -56,6 +56,16 @@ #include "intel_drv.h" #include "i915_drv.h" +static bool psr_global_enabled(enum i915_psr_debugfs_mode mode) +{ + if (mode == PSR_DEBUGFS_MODE_DEFAULT) + return i915_modparams.enable_psr; + else if (mode == PSR_DEBUGFS_MODE_DISABLED) + return false; + else + return true; +} + void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug) { u32 debug_mask, mask; @@ -471,11 +481,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!CAN_PSR(dev_priv)) return; - if (!i915_modparams.enable_psr) { - DRM_DEBUG_KMS("PSR disable by flag\n"); - return; - } - /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms with DDI implementation of PSR have different @@ -517,7 +522,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, crtc_state->has_psr = true; crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); - DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); + + if (psr_global_enabled(dev_priv->psr.debugfs_mode)) + DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); + else + DRM_DEBUG_KMS("PSR disable by flag\n"); } static void intel_psr_activate(struct intel_dp *intel_dp) @@ -589,6 +598,22 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, } } +static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, + const struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = dev_priv->psr.dp; + + if (dev_priv->psr.enabled) + return; + + intel_psr_setup_vsc(intel_dp, crtc_state); + intel_psr_enable_sink(intel_dp); + intel_psr_enable_source(intel_dp, crtc_state); + dev_priv->psr.enabled = true; + + intel_psr_activate(intel_dp); +} + /** * intel_psr_enable - Enable PSR * @intel_dp: Intel DP @@ -611,7 +636,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, WARN_ON(dev_priv->drrs.dp); mutex_lock(&dev_priv->psr.lock); - if (dev_priv->psr.enabled) { + if (dev_priv->psr.dp) { DRM_DEBUG_KMS("PSR already in use\n"); goto unlock; } @@ -619,12 +644,10 @@ void intel_psr_enable(struct intel_dp *intel_dp, dev_priv->psr.psr2_enabled = crtc_state->has_psr2; dev_priv->psr.busy_frontbuffer_bits = 0; - intel_psr_setup_vsc(intel_dp, crtc_state); - intel_psr_enable_sink(intel_dp); - intel_psr_enable_source(intel_dp, crtc_state); - dev_priv->psr.enabled = intel_dp; + dev_priv->psr.dp = intel_dp; - intel_psr_activate(intel_dp); + if (psr_global_enabled(dev_priv->psr.debugfs_mode)) + intel_psr_enable_locked(dev_priv, crtc_state); unlock: mutex_unlock(&dev_priv->psr.lock); @@ -688,7 +711,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); - dev_priv->psr.enabled = NULL; + dev_priv->psr.enabled = false; } /** @@ -712,7 +735,14 @@ void intel_psr_disable(struct intel_dp *intel_dp, return; mutex_lock(&dev_priv->psr.lock); + if (intel_dp != dev_priv->psr.dp) { + mutex_unlock(&dev_priv->psr.lock); + return; + } + intel_psr_disable_locked(intel_dp); + + dev_priv->psr.dp = NULL; mutex_unlock(&dev_priv->psr.lock); cancel_work_sync(&dev_priv->psr.work); } @@ -756,13 +786,11 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) { - struct intel_dp *intel_dp; i915_reg_t reg; u32 mask; int err; - intel_dp = dev_priv->psr.enabled; - if (!intel_dp) + if (!dev_priv->psr.enabled) return false; if (dev_priv->psr.psr2_enabled) { @@ -784,6 +812,89 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) return err == 0 && dev_priv->psr.enabled; } +static struct drm_crtc * +find_idle_crtc_for_encoder(struct drm_encoder *encoder, + struct drm_modeset_acquire_ctx *ctx) +{ + struct drm_connector_list_iter conn_iter; + struct drm_device *dev = encoder->dev; + struct drm_connector *connector; + struct drm_crtc *crtc; + bool found = false; + int ret; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) + if (connector->state->best_encoder == encoder) { + found = true; + break; + } + drm_connector_list_iter_end(&conn_iter); + + if (WARN_ON(!found)) + return ERR_PTR(-EINVAL); + + crtc = connector->state->crtc; + ret = drm_modeset_lock(&crtc->mutex, ctx); + if (ret) + return ERR_PTR(ret); + + if (connector->state->commit) + ret = wait_for_completion_interruptible(&connector->state->commit->hw_done); + if (!ret && crtc->state->commit) + ret = wait_for_completion_interruptible(&crtc->state->commit->hw_done); + if (ret) + return ERR_PTR(ret); + + return crtc; +} + +int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, + struct drm_modeset_acquire_ctx *ctx, + enum i915_psr_debugfs_mode mode) +{ + struct drm_device *dev = &dev_priv->drm; + struct drm_encoder *encoder; + struct drm_crtc *crtc; + int ret; + bool enable; + + ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx); + if (ret) + return ret; + + enable = psr_global_enabled(mode); + + mutex_lock(&dev_priv->psr.lock); + + do { + if (!dev_priv->psr.dp) { + dev_priv->psr.debugfs_mode = mode; + goto end; + } + encoder = &dp_to_dig_port(dev_priv->psr.dp)->base.base; + mutex_unlock(&dev_priv->psr.lock); + + crtc = find_idle_crtc_for_encoder(encoder, ctx); + if (IS_ERR(crtc)) + return PTR_ERR(crtc); + + mutex_lock(&dev_priv->psr.lock); + } while (dev_priv->psr.dp != enc_to_intel_dp(encoder)); + + if (!enable) + intel_psr_disable_locked(enc_to_intel_dp(encoder)); + + dev_priv->psr.debugfs_mode = mode; + + if (enable) + intel_psr_enable_locked(dev_priv, to_intel_crtc_state(crtc->state)); + +end: + mutex_unlock(&dev_priv->psr.lock); + return ret; +} + static void intel_psr_work(struct work_struct *work) { struct drm_i915_private *dev_priv = @@ -811,7 +922,8 @@ static void intel_psr_work(struct work_struct *work) if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) goto unlock; - intel_psr_activate(dev_priv->psr.enabled); + intel_psr_activate(dev_priv->psr.dp +); unlock: mutex_unlock(&dev_priv->psr.lock); } @@ -866,7 +978,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, return; } - crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; + crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc; pipe = to_intel_crtc(crtc)->pipe; frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); @@ -909,7 +1021,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, return; } - crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; + crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc; pipe = to_intel_crtc(crtc)->pipe; frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); @@ -971,6 +1083,8 @@ void intel_psr_init(struct drm_i915_private *dev_priv) /* For new platforms let's respect VBT back again */ dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; + dev_priv->psr.debugfs_mode = PSR_DEBUGFS_MODE_DEFAULT; + INIT_WORK(&dev_priv->psr.work, intel_psr_work); mutex_init(&dev_priv->psr.lock); } @@ -991,7 +1105,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) mutex_lock(&psr->lock); - if (psr->enabled != intel_dp) + if (!psr->enabled || psr->dp != intel_dp) goto exit; if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { -- 2.18.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
