The only thing left from *_display_core_init when display is disabled
is the skl_pch_reset_handshake() that is already handling display
enabled and disabled. And *_display_core_uninit() also was left
to disable DC.
If more power savings is required, we could disable the power wells
that BIOS enable.
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 01e0c8e82fcf..8a84c77a1a88 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3292,6 +3292,9 @@ static void skl_display_core_init(struct drm_i915_private
*dev_priv,
/* enable PCH reset handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
@@ -3318,6 +3321,9 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
skl_uninit_cdclk(dev_priv);
@@ -3357,6 +3363,9 @@ void bxt_display_core_init(struct drm_i915_private
*dev_priv,
*/
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* Enable PG1 */
mutex_lock(&power_domains->lock);
@@ -3380,6 +3389,9 @@ void bxt_display_core_uninit(struct drm_i915_private
*dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
bxt_uninit_cdclk(dev_priv);
@@ -3478,6 +3490,9 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
/* 1. Enable PCH Reset Handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
@@ -3522,7 +3537,10 @@ static void cnl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv);
@@ -3561,6 +3579,9 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
/* 1. Enable PCH reset handshake. */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
val = I915_READ(ICL_PHY_MISC(port));
@@ -3607,7 +3628,10 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
icl_dbuf_disable(dev_priv);
@@ -3773,11 +3797,11 @@ void intel_power_domains_init_hw(struct
drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
--
2.18.0
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