According to BSpec, for ILK and SNB those bits must be programmed to 1 before enabling VGA display and kept enable while VGA display is enabled. It says also it is safe to have it as 1 even when VGA display is disabled.
Signed-off-by: Rodrigo Vivi <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2a5ea6..8314124 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -816,6 +816,8 @@ #define ILK_FBC_RT_VALID (1<<0) #define ILK_DISPLAY_CHICKEN1 0x42000 +#define ILK_VRD_REQ_STALL_DIS (1<<31) +#define ILK_VRD_REQ_STALL_TH (1<<29) #define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index abfff29..dfb1be7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3381,6 +3381,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_VRD_REQ_STALL_DIS | ILK_VRD_REQ_STALL_TH); + /* Required for FBC */ dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | @@ -3470,6 +3474,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_VRD_REQ_STALL_DIS | ILK_VRD_REQ_STALL_TH); + I915_WRITE(ILK_DISPLAY_CHICKEN2, I915_READ(ILK_DISPLAY_CHICKEN2) | ILK_ELPIN_409_SELECT); -- 1.7.11.7 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
