On Thu, 2018-09-20 at 23:01 +0000, Souza, Jose wrote:
> On Thu, 2018-09-20 at 15:54 -0700, Rodrigo Vivi wrote:
> > On Thu, Sep 20, 2018 at 01:43:25PM -0700, José Roberto de Souza
> > wrote:
> > > This WA also works fine for PSR2, triggering a selective update
> > > when
> > > possible.
> >
> > Oh! really?! It didn't work when I chacked on my CNL,
> > but we probably had other bugs back there...
>
> Tested in WHL and ICL, I will give a try in CNL.
>
> >
> > Thanks for finding this
> >
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
I haven't checked myself but from what I understand it should work
Acked-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> >
> >
> >
> > >
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_psr.c | 24 ++++++++++--------------
> > > 1 file changed, 10 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 84b512426514..cf9d6e965697 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -1026,20 +1026,16 @@ void intel_psr_flush(struct
> > > drm_i915_private *dev_priv,
> > >
> > > /* By definition flush = invalidate + flush */
> > > if (frontbuffer_bits) {
> > > - if (dev_priv->psr.psr2_enabled) {
> > > - intel_psr_exit(dev_priv);
> > > - } else {
> > > - /*
> > > - * Display WA #0884: all
> > > - * This documented WA for bxt can be
> > > safely
> > > applied
> > > - * broadly so we can force HW tracking
> > > to exit
> > > PSR
> > > - * instead of disabling and re-enabling.
> > > - * Workaround tells us to write 0 to
> > > CUR_SURFLIVE_A,
> > > - * but it makes more sense write to the
> > > current
> > > active
> > > - * pipe.
> > > - */
> > > - I915_WRITE(CURSURFLIVE(pipe), 0);
> > > - }
> > > + /*
> > > + * Display WA #0884: all
> > > + * This documented WA for bxt can be safely
> > > applied
> > > + * broadly so we can force HW tracking to exit
> > > PSR
> > > + * instead of disabling and re-enabling.
> > > + * Workaround tells us to write 0 to
> > > CUR_SURFLIVE_A,
> > > + * but it makes more sense write to the current
> > > active
> > > + * pipe.
> > > + */
> > > + I915_WRITE(CURSURFLIVE(pipe), 0);
> > > }
> > >
> > > if (!dev_priv->psr.active && !dev_priv-
> > > > psr.busy_frontbuffer_bits)
> > >
> > > --
> > > 2.19.0
> > >
>
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