On Thu, 20 Sep 2018, José Roberto de Souza <[email protected]> wrote: > ICL spec states that this bit is now reserved. > > Spec: 7722 > > Cc: Dhinakaran Pandiyan <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++------ > 2 files changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4948b352bf4c..4dd5290a3b95 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4195,7 +4195,7 @@ enum { > #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) > #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) > #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) > -#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) > +#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ > */ > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ > > #define EDP_PSR2_CTL _MMIO(0x6f900) > @@ -4232,7 +4232,7 @@ enum { > #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) > #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) > #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) > -#define PSR_EVENT_REGISTER_UPDATE (1 << 5) > +#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ > #define PSR_EVENT_HDCP_ENABLE (1 << 4) > #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) > #define PSR_EVENT_VBI_ENABLE (1 << 2) > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 358bbcd3b5f3..6f3c6f0c539f 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -558,6 +558,7 @@ static void intel_psr_enable_source(struct intel_dp > *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + u32 mask; > > /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ > * use hardcoded values PSR AUX transactions > @@ -583,12 +584,16 @@ static void intel_psr_enable_source(struct intel_dp > *intel_dp, > * runtime_pm besides preventing other hw tracking issues now we > * can rely on frontbuffer tracking. > */ > - I915_WRITE(EDP_PSR_DEBUG, > - EDP_PSR_DEBUG_MASK_MEMUP | > - EDP_PSR_DEBUG_MASK_HPD | > - EDP_PSR_DEBUG_MASK_LPSP | > - EDP_PSR_DEBUG_MASK_DISP_REG_WRITE | > - EDP_PSR_DEBUG_MASK_MAX_SLEEP); > + mask = EDP_PSR_DEBUG_MASK_MEMUP | > + EDP_PSR_DEBUG_MASK_HPD | > + EDP_PSR_DEBUG_MASK_LPSP | > + EDP_PSR_DEBUG_MASK_DISP_REG_WRITE | > + EDP_PSR_DEBUG_MASK_MAX_SLEEP; > + > + if (INTEL_GEN(dev_priv) >= 11) > + mask &= ~EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
Seems better to |= this on gen < 11 rather than &= ~ on gen >= 11. BR, Jani. > + > + I915_WRITE(EDP_PSR_DEBUG, mask); > } > > static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
