On Thu, 2018-10-04 at 20:01 -0700, Dhinakaran Pandiyan wrote: > The hardware can start selective update following capture of a full > frame > in the remote frame buffer, there is no need to wait any longer. Set > "Frames Before SU Entry" bitfield to the default value of 1. > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 83528647b40b..105b7ea2cd98 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -424,6 +424,7 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > > idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency > + 1); > val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; > + val |= EDP_PSR2_FRAME_BEFORE_SU(1);
I guess 0 would the right value, setting to 1 feels like it would wait 1 frame after a flip/front buffer modfication to do a SU. I will run some tests changing EDP_PSR2_IDLE_FRAME_SHIFT and EDP_PSR2_FRAME_BEFORE_SU. > > /* FIXME: selective update is probably totally broken because > it doesn't > * mesh at all with our frontbuffer tracking. And the hw alone > isn't > @@ -432,8 +433,6 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > val |= EDP_Y_COORDINATE_ENABLE; > > - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency > + 1); > - > if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && > dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) > val |= EDP_PSR2_TP2_TIME_50us; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
