On Fri, Oct 26, 2018 at 05:32:45PM +0200, Tomasz Lis wrote: > The MOCS tables are going to be very similar across platforms. > > To reduce the amount of copied code, this patch rips the common part and > puts it into a definition valid for all gen9 platforms. > > Signed-off-by: Tomasz Lis <[email protected]> > Suggested-by: Lucas De Marchi <[email protected]> > Cc: Joonas Lahtinen <[email protected]> > Cc: Chris Wilson <[email protected]> > Cc: Daniele Ceraolo Spurio <[email protected]> > Cc: Lucas De Marchi <[email protected]>
yeah, this is what I was suggesting. Not sure if in future this will blow out of proportion - we need to remember that each table is 64 entries of this struct in the ro section. If this happens, then maybe we will need to change the approach and move the idx inside the entry rather than 64-entry arrays. I think this can be left for later if/when there's need. Right now this improves the status quo IMO. Reviewed-by: Lucas De Marchi <[email protected]> thanks Lucas De Marchi > --- > drivers/gpu/drm/i915/intel_mocs.c | 61 > ++++++++++++++------------------------- > 1 file changed, 22 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c > b/drivers/gpu/drm/i915/intel_mocs.c > index 77e9871..76aed59 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -96,26 +96,29 @@ struct drm_i915_mocs_table { > * may only be updated incrementally by adding entries at the > * end. > */ > -static const struct drm_i915_mocs_entry skylake_mocs_table[] = { > - [I915_MOCS_UNCACHED] = { > - /* 0x00000009 */ > - .control_value = LE_CACHEABILITY(LE_UC) | > - LE_TGT_CACHE(LE_TC_LLC_ELLC) | > - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > - LE_PFM(0) | LE_SCF(0), > > - /* 0x0010 */ > - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > - }, > - [I915_MOCS_PTE] = { > - /* 0x00000038 */ > - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | > - LE_TGT_CACHE(LE_TC_LLC_ELLC) | > - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > - LE_PFM(0) | LE_SCF(0), > - /* 0x0030 */ > - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > +#define GEN9_MOCS_TABLE \ > + [I915_MOCS_UNCACHED] = { \ > + /* 0x00000009 */ \ > + .control_value = LE_CACHEABILITY(LE_UC) | \ > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | \ > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \ > + LE_PFM(0) | LE_SCF(0), \ > + /* 0x0010 */ \ > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \ > + }, \ > + [I915_MOCS_PTE] = { \ > + /* 0x00000038 */ \ > + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \ > + LE_TGT_CACHE(LE_TC_LLC_ELLC) | \ > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \ > + LE_PFM(0) | LE_SCF(0), \ > + /* 0x0030 */ \ > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \ > }, > + > +static const struct drm_i915_mocs_entry skylake_mocs_table[] = { > + GEN9_MOCS_TABLE > [I915_MOCS_CACHED] = { > /* 0x0000003b */ > .control_value = LE_CACHEABILITY(LE_WB) | > @@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry > skylake_mocs_table[] = { > > /* NOTE: the LE_TGT_CACHE is not used on Broxton */ > static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > - [I915_MOCS_UNCACHED] = { > - /* 0x00000009 */ > - .control_value = LE_CACHEABILITY(LE_UC) | > - LE_TGT_CACHE(LE_TC_LLC_ELLC) | > - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > - LE_PFM(0) | LE_SCF(0), > - > - /* 0x0010 */ > - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > - }, > - [I915_MOCS_PTE] = { > - /* 0x00000038 */ > - .control_value = LE_CACHEABILITY(LE_PAGETABLE) | > - LE_TGT_CACHE(LE_TC_LLC_ELLC) | > - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > - LE_PFM(0) | LE_SCF(0), > - > - /* 0x0030 */ > - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > - }, > + GEN9_MOCS_TABLE > [I915_MOCS_CACHED] = { > /* 0x00000039 */ > .control_value = LE_CACHEABILITY(LE_UC) | > LE_TGT_CACHE(LE_TC_LLC_ELLC) | > LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > LE_PFM(0) | LE_SCF(0), > - > /* 0x0030 */ > .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > }, > -- > 2.7.4 > _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
