On Thu, Oct 25, 2018 at 05:56:36PM -0700, Rodrigo Vivi wrote: > While checking the opportunity to add a display_gen > check to allow glk and cnl to be on same bucket I noticed > these FIXME cases here. > > So I got the confirmation from HW architect that we actually > never needed this workaround. > > "GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk."
Cool. Reviewed-by: Ville Syrjälä <[email protected]> > > So, this reverts commit 97f55ca5b662 ("drm/i915/glk: limit pixel > clock to 99% of cdclk workaround") > > Fixes: 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk > workaround") > > Cc: Ville Syrjälä <[email protected]> > Cc: Madhav Chauhan <[email protected]> > Cc: Jani Nikula <[email protected]> > Cc: Clinton Taylor <[email protected]> > Cc: Arthur J Runyan <[email protected]> > Signed-off-by: Rodrigo Vivi <[email protected]> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 18 ++---------------- > 1 file changed, 2 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > b/drivers/gpu/drm/i915/intel_cdclk.c > index 29075c763428..8d74276029e6 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, > static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, > int pixel_rate) > { > - if (INTEL_GEN(dev_priv) >= 10) > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > return DIV_ROUND_UP(pixel_rate, 2); > - else if (IS_GEMINILAKE(dev_priv)) > - /* > - * FIXME: Avoid using a pixel clock that is more than 99% of > the cdclk > - * as a temporary workaround. Use a higher cdclk instead. (Note > that > - * intel_compute_max_dotclk() limits the max pixel clock to 99% > of max > - * cdclk.) > - */ > - return DIV_ROUND_UP(pixel_rate * 100, 2 * 99); > else if (IS_GEN9(dev_priv) || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return pixel_rate; > @@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct > drm_i915_private *dev_priv) > { > int max_cdclk_freq = dev_priv->max_cdclk_freq; > > - if (INTEL_GEN(dev_priv) >= 10) > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > return 2 * max_cdclk_freq; > - else if (IS_GEMINILAKE(dev_priv)) > - /* > - * FIXME: Limiting to 99% as a temporary workaround. See > - * intel_min_cdclk() for details. > - */ > - return 2 * max_cdclk_freq * 99 / 100; > else if (IS_GEN9(dev_priv) || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return max_cdclk_freq; > -- > 2.19.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
