Hello,
row_index and column_index are unsigned, so in the last line shown
they will not be less than 0.
julia
---------- Forwarded message ----------
Date: Wed, 28 Nov 2018 19:43:30 +0800
From: kbuild test robot <l...@intel.com>
To: kbu...@01.org
Cc: Julia Lawall <julia.law...@lip6.fr>
Subject: Re: [Intel-gfx] [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC
params
CC: kbuild-...@01.org
In-Reply-To: <20181127214125.17658-10-manasi.d.nav...@intel.com>
References: <20181127214125.17658-10-manasi.d.nav...@intel.com>
TO: Manasi Navare <manasi.d.nav...@intel.com>
CC: intel-gfx@lists.freedesktop.org
CC:
Hi Gaurav,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20181127]
[cannot apply to v4.20-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095026
base: git://anongit.freedesktop.org/drm-intel for-linux-next
:::::: branch date: 10 hours ago
:::::: commit date: 10 hours ago
>> drivers/gpu/drm/i915/intel_vdsc.c:404:22-34: WARNING: Unsigned expression
>> compared with zero: column_index < 0
>> drivers/gpu/drm/i915/intel_vdsc.c:404:5-14: WARNING: Unsigned expression
>> compared with zero: row_index < 0
#
https://github.com/0day-ci/linux/commit/5b6895999d5a84b154fcd49dc3a91d71897d03ec
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 5b6895999d5a84b154fcd49dc3a91d71897d03ec
vim +404 drivers/gpu/drm/i915/intel_vdsc.c
5b689599 Gaurav K Singh 2018-11-27 319
5b689599 Gaurav K Singh 2018-11-27 320 int intel_dp_compute_dsc_params(struct
intel_dp *intel_dp,
5b689599 Gaurav K Singh 2018-11-27 321 struct
intel_crtc_state *pipe_config)
5b689599 Gaurav K Singh 2018-11-27 322 {
5b689599 Gaurav K Singh 2018-11-27 323 struct drm_dsc_config *vdsc_cfg
= &pipe_config->dp_dsc_cfg;
5b689599 Gaurav K Singh 2018-11-27 324 u16 compressed_bpp =
pipe_config->dsc_params.compressed_bpp;
5b689599 Gaurav K Singh 2018-11-27 325 u8 i = 0;
5b689599 Gaurav K Singh 2018-11-27 326 u8 row_index = 0;
5b689599 Gaurav K Singh 2018-11-27 327 u8 column_index = 0;
5b689599 Gaurav K Singh 2018-11-27 328 u8 line_buf_depth = 0;
5b689599 Gaurav K Singh 2018-11-27 329
5b689599 Gaurav K Singh 2018-11-27 330 vdsc_cfg->pic_width =
pipe_config->base.adjusted_mode.crtc_hdisplay;
5b689599 Gaurav K Singh 2018-11-27 331 vdsc_cfg->pic_height =
pipe_config->base.adjusted_mode.crtc_vdisplay;
5b689599 Gaurav K Singh 2018-11-27 332 vdsc_cfg->slice_width =
DIV_ROUND_UP(vdsc_cfg->pic_width,
5b689599 Gaurav K Singh 2018-11-27 333
pipe_config->dsc_params.slice_count);
5b689599 Gaurav K Singh 2018-11-27 334 /*
5b689599 Gaurav K Singh 2018-11-27 335 * Slice Height of 8 works for
all currently available panels. So start
5b689599 Gaurav K Singh 2018-11-27 336 * with that if pic_height is
an integral multiple of 8.
5b689599 Gaurav K Singh 2018-11-27 337 * Eventually add logic to try
multiple slice heights.
5b689599 Gaurav K Singh 2018-11-27 338 */
5b689599 Gaurav K Singh 2018-11-27 339 if (vdsc_cfg->pic_height % 8 ==
0)
5b689599 Gaurav K Singh 2018-11-27 340 vdsc_cfg->slice_height
= 8;
5b689599 Gaurav K Singh 2018-11-27 341 else if (vdsc_cfg->pic_height %
4 == 0)
5b689599 Gaurav K Singh 2018-11-27 342 vdsc_cfg->slice_height
= 4;
5b689599 Gaurav K Singh 2018-11-27 343 else
5b689599 Gaurav K Singh 2018-11-27 344 vdsc_cfg->slice_height
= 2;
5b689599 Gaurav K Singh 2018-11-27 345
5b689599 Gaurav K Singh 2018-11-27 346 /* Values filled from DSC Sink
DPCD */
5b689599 Gaurav K Singh 2018-11-27 347 vdsc_cfg->dsc_version_major =
5b689599 Gaurav K Singh 2018-11-27 348
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
5b689599 Gaurav K Singh 2018-11-27 349 DP_DSC_MAJOR_MASK) >>
DP_DSC_MAJOR_SHIFT;
5b689599 Gaurav K Singh 2018-11-27 350 vdsc_cfg->dsc_version_minor =
5b689599 Gaurav K Singh 2018-11-27 351
min(DSC_SUPPORTED_VERSION_MIN,
5b689599 Gaurav K Singh 2018-11-27 352
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
5b689599 Gaurav K Singh 2018-11-27 353 DP_DSC_MINOR_MASK)
>> DP_DSC_MINOR_SHIFT);
5b689599 Gaurav K Singh 2018-11-27 354
5b689599 Gaurav K Singh 2018-11-27 355 vdsc_cfg->convert_rgb =
intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
5b689599 Gaurav K Singh 2018-11-27 356 DP_DSC_RGB;
5b689599 Gaurav K Singh 2018-11-27 357
5b689599 Gaurav K Singh 2018-11-27 358 line_buf_depth =
drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
5b689599 Gaurav K Singh 2018-11-27 359 if (!line_buf_depth) {
5b689599 Gaurav K Singh 2018-11-27 360 DRM_DEBUG_KMS("DSC Sink
Line Buffer Depth invalid\n");
5b689599 Gaurav K Singh 2018-11-27 361 return -EINVAL;
5b689599 Gaurav K Singh 2018-11-27 362 }
5b689599 Gaurav K Singh 2018-11-27 363 if (vdsc_cfg->dsc_version_minor
== 2)
5b689599 Gaurav K Singh 2018-11-27 364
vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
5b689599 Gaurav K Singh 2018-11-27 365
DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
5b689599 Gaurav K Singh 2018-11-27 366 else
5b689599 Gaurav K Singh 2018-11-27 367
vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
5b689599 Gaurav K Singh 2018-11-27 368
DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
5b689599 Gaurav K Singh 2018-11-27 369
5b689599 Gaurav K Singh 2018-11-27 370 /* Gen 11 does not support
YCbCr */
5b689599 Gaurav K Singh 2018-11-27 371 vdsc_cfg->enable422 = false;
5b689599 Gaurav K Singh 2018-11-27 372 /* Gen 11 does not support VBR
*/
5b689599 Gaurav K Singh 2018-11-27 373 vdsc_cfg->vbr_enable = false;
5b689599 Gaurav K Singh 2018-11-27 374 vdsc_cfg->block_pred_enable =
5b689599 Gaurav K Singh 2018-11-27 375
intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
5b689599 Gaurav K Singh 2018-11-27 376
DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
5b689599 Gaurav K Singh 2018-11-27 377
5b689599 Gaurav K Singh 2018-11-27 378 /* Gen 11 only supports
integral values of bpp */
5b689599 Gaurav K Singh 2018-11-27 379 vdsc_cfg->bits_per_pixel =
compressed_bpp << 4;
5b689599 Gaurav K Singh 2018-11-27 380 vdsc_cfg->bits_per_component =
pipe_config->pipe_bpp / 3;
5b689599 Gaurav K Singh 2018-11-27 381
5b689599 Gaurav K Singh 2018-11-27 382 for (i = 0; i <
DSC_NUM_BUF_RANGES - 1; i++) {
5b689599 Gaurav K Singh 2018-11-27 383 /*
5b689599 Gaurav K Singh 2018-11-27 384 * six 0s are appended
to the lsb of each threshold value
5b689599 Gaurav K Singh 2018-11-27 385 * internally in h/w.
5b689599 Gaurav K Singh 2018-11-27 386 * Only 8 bits are
allowed for programming RcBufThreshold
5b689599 Gaurav K Singh 2018-11-27 387 */
5b689599 Gaurav K Singh 2018-11-27 388
vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
5b689599 Gaurav K Singh 2018-11-27 389 }
5b689599 Gaurav K Singh 2018-11-27 390
5b689599 Gaurav K Singh 2018-11-27 391 /*
5b689599 Gaurav K Singh 2018-11-27 392 * For 6bpp, RC Buffer
threshold 12 and 13 need a different value
5b689599 Gaurav K Singh 2018-11-27 393 * as per C Model
5b689599 Gaurav K Singh 2018-11-27 394 */
5b689599 Gaurav K Singh 2018-11-27 395 if (compressed_bpp == 6) {
5b689599 Gaurav K Singh 2018-11-27 396
vdsc_cfg->rc_buf_thresh[12] = 0x7C;
5b689599 Gaurav K Singh 2018-11-27 397
vdsc_cfg->rc_buf_thresh[13] = 0x7D;
5b689599 Gaurav K Singh 2018-11-27 398 }
5b689599 Gaurav K Singh 2018-11-27 399
5b689599 Gaurav K Singh 2018-11-27 400 row_index =
get_row_index_for_rc_params(compressed_bpp);
5b689599 Gaurav K Singh 2018-11-27 401 column_index =
5b689599 Gaurav K Singh 2018-11-27 402
get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
5b689599 Gaurav K Singh 2018-11-27 403
5b689599 Gaurav K Singh 2018-11-27 @404 if (row_index < 0 ||
column_index < 0)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
