On Fri, 8 Feb 2013 17:35:18 -0200 Paulo Zanoni <przan...@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com> > > On ILK/SNB all we need to do is to enable the "poison" bit, but on > IVB/HSW we need to enable the CPU error interrupt register, which is > responsible not only for poison interrupts, but also other things. > This includes the "unclaimed register" interrupt, so on the IVB irq > handler we now need to: (i) check whether the interrupt was triggered by an > unclaimed register and (ii) mask the error interrupt bit so we don't > risk generating "unclaimed register" interrupts form inside the > interrupt handler. > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com> > --- OTOH there's nothing the user can do about it... so we might do a WARN_ONCE or something here instead. But even then, I'm not sure there's much *we* can do about these, as they indicate a corruption in the communication between the CPU and PCH. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
