On Mon, Feb 04, 2019 at 02:25:38PM -0800, Rodrigo Vivi wrote:
> First of all GMCH can be considered a feature by itself
> since it is a chip present in some platforms that connects
> the IA processor to memory and other components in PC.
VLV/CHV don't have a GMCH. What they have is display engine derived
from the old GMCH era design.
>
> Also with the introduction of display block at device info,
> we got a redundant definition:
>
> .display.has_gmch_display = 1,
>
> So, let's clean up things a bit and use the standardized
> way of has_feature on displays side.
>
> No functional change and no manual interaction to generate
> this patch.
>
> It is only:
>
> sed -si -e 's/has_gmch_display/has_gmch/g' \
> -e 's/HAS_GMCH_DISPLAY/HAS_GMCH/g' drivers/gpu/drm/i915/*{c,h}
>
> Cc: José Roberto de Souza <[email protected]>
> Cc: Ville Syrjälä <[email protected]>
> Signed-off-by: Rodrigo Vivi <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 10 ++++----
> drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
> drivers/gpu/drm/i915/intel_color.c | 6 ++---
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++-----------
> drivers/gpu/drm/i915/intel_dp.c | 12 +++++-----
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 ++---
> drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> drivers/gpu/drm/i915/intel_hotplug.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> drivers/gpu/drm/i915/vlv_dsi.c | 4 ++--
> 13 files changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index fa2c226fc779..eff2e7f6762c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3728,7 +3728,7 @@ static int spr_wm_latency_open(struct inode *inode,
> struct file *file)
> {
> struct drm_i915_private *dev_priv = inode->i_private;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> return -ENODEV;
>
> return single_open(file, spr_wm_latency_show, dev_priv);
> @@ -3738,7 +3738,7 @@ static int cur_wm_latency_open(struct inode *inode,
> struct file *file)
> {
> struct drm_i915_private *dev_priv = inode->i_private;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> return -ENODEV;
>
> return single_open(file, cur_wm_latency_show, dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 534e52e3a8da..9f6954512547 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2490,7 +2490,7 @@ static inline unsigned int i915_sg_segment_size(void)
>
> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
> -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) &&
> INTEL_GEN(dev_priv) >= 7)
> +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) &&
> INTEL_GEN(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> @@ -2570,7 +2570,7 @@ static inline unsigned int i915_sg_segment_size(void)
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> -#define HAS_GMCH_DISPLAY(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_gmch_display)
> +#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
> #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 5d05572c9ff4..cd5a779289c2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -89,7 +89,7 @@
> .num_pipes = 1, \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> - .display.has_gmch_display = 1, \
> + .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> @@ -130,7 +130,7 @@ static const struct intel_device_info intel_i865g_info = {
> #define GEN3_FEATURES \
> GEN(3), \
> .num_pipes = 2, \
> - .display.has_gmch_display = 1, \
> + .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .ring_mask = RENDER_RING, \
> .has_snoop = true, \
> @@ -207,7 +207,7 @@ static const struct intel_device_info intel_pineview_info
> = {
> GEN(4), \
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> - .display.has_gmch_display = 1, \
> + .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> .ring_mask = RENDER_RING, \
> .has_snoop = true, \
> @@ -383,7 +383,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> .num_pipes = 2,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> - .display.has_gmch_display = 1,
> + .display.has_gmch = 1,
> .display.has_hotplug = 1,
> .ppgtt = INTEL_PPGTT_FULL,
> .has_snoop = true,
> @@ -475,7 +475,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> .has_logical_ring_contexts = 1,
> - .display.has_gmch_display = 1,
> + .display.has_gmch = 1,
> .ppgtt = INTEL_PPGTT_FULL,
> .has_reset_engine = 1,
> .has_snoop = true,
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c
> b/drivers/gpu/drm/i915/i915_suspend.c
> index f18afa2bac8d..d2f2a9c2fabd 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -86,7 +86,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
> } else if (IS_GEN(dev_priv, 2)) {
> for (i = 0; i < 7; i++)
> dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> - } else if (HAS_GMCH_DISPLAY(dev_priv)) {
> + } else if (HAS_GMCH(dev_priv)) {
> for (i = 0; i < 16; i++) {
> dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> @@ -131,7 +131,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
> } else if (IS_GEN(dev_priv, 2)) {
> for (i = 0; i < 7; i++)
> I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> - } else if (HAS_GMCH_DISPLAY(dev_priv)) {
> + } else if (HAS_GMCH(dev_priv)) {
> for (i = 0; i < 16; i++) {
> I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 4b0044cdcf1a..31fa599b0d61 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -321,7 +321,7 @@ static void i9xx_load_luts_internal(struct
> intel_crtc_state *crtc_state,
> enum pipe pipe = crtc->pipe;
> int i;
>
> - if (HAS_GMCH_DISPLAY(dev_priv)) {
> + if (HAS_GMCH(dev_priv)) {
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> assert_dsi_pll_enabled(dev_priv);
> else
> @@ -336,7 +336,7 @@ static void i9xx_load_luts_internal(struct
> intel_crtc_state *crtc_state,
> (drm_color_lut_extract(lut[i].green, 8) << 8) |
> drm_color_lut_extract(lut[i].blue, 8);
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> I915_WRITE(PALETTE(pipe, i), word);
> else
> I915_WRITE(LGC_PALETTE(pipe, i), word);
> @@ -345,7 +345,7 @@ static void i9xx_load_luts_internal(struct
> intel_crtc_state *crtc_state,
> for (i = 0; i < 256; i++) {
> u32 word = (i << 16) | (i << 8) | i;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> I915_WRITE(PALETTE(pipe, i), word);
> else
> I915_WRITE(LGC_PALETTE(pipe, i), word);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 7bf09cef591a..e8b8661df746 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -115,7 +115,7 @@ enum intel_ppgtt {
> func(has_ddi); \
> func(has_dp_mst); \
> func(has_fbc); \
> - func(has_gmch_display); \
> + func(has_gmch); \
> func(has_hotplug); \
> func(has_ipc); \
> func(has_overlay); \
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index df7a7a310f2f..663987917fbd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1805,7 +1805,7 @@ static void intel_enable_pipe(const struct
> intel_crtc_state *new_crtc_state)
> * a plane. On ILK+ the pipe PLLs are integrated, so we don't
> * need the check.
> */
> - if (HAS_GMCH_DISPLAY(dev_priv)) {
> + if (HAS_GMCH(dev_priv)) {
> if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> assert_dsi_pll_enabled(dev_priv);
> else
> @@ -2094,7 +2094,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> * complicated than this. For example, Cherryview appears quite
> * happy to scanout from anywhere within its global aperture.
> */
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> pinctl |= PIN_MAPPABLE;
>
> vma = i915_gem_object_pin_to_display_plane(obj,
> @@ -3195,7 +3195,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>
> - if (!HAS_GMCH_DISPLAY(dev_priv)) {
> + if (!HAS_GMCH(dev_priv)) {
> return 32*1024;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> if (modifier == I915_FORMAT_MOD_X_TILED)
> @@ -3771,7 +3771,7 @@ __intel_display_resume(struct drm_device *dev,
> }
>
> /* ignore any reset values/BIOS leftovers in the WM registers */
> - if (!HAS_GMCH_DISPLAY(to_i915(dev)))
> + if (!HAS_GMCH(to_i915(dev)))
> to_intel_atomic_state(state)->skip_intermediate_wm = true;
>
> ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
> @@ -5294,7 +5294,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc
> *crtc)
> * event which is after the vblank start event, so we need to have a
> * wait-for-vblank between disabling the plane and the pipe.
> */
> - if (HAS_GMCH_DISPLAY(dev_priv) &&
> + if (HAS_GMCH(dev_priv) &&
> intel_set_memory_cxsr(dev_priv, false))
> intel_wait_for_vblank(dev_priv, pipe);
> }
> @@ -5431,7 +5431,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
> * event which is after the vblank start event, so we need to have a
> * wait-for-vblank between disabling the plane and the pipe.
> */
> - if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
> + if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
> pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
> intel_wait_for_vblank(dev_priv, crtc->pipe);
>
> @@ -6705,7 +6705,7 @@ static void intel_crtc_compute_pixel_rate(struct
> intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> /* FIXME calculate proper pipe pixel rate for GMCH pfit */
> crtc_state->pixel_rate =
> crtc_state->base.adjusted_mode.crtc_clock;
> @@ -9814,7 +9814,7 @@ static u32 intel_cursor_base(const struct
> intel_plane_state *plane_state)
> base += plane_state->color_plane[0].offset;
>
> /* ILK+ do this automagically */
> - if (HAS_GMCH_DISPLAY(dev_priv) &&
> + if (HAS_GMCH(dev_priv) &&
> plane_state->base.rotation & DRM_MODE_ROTATE_180)
> base += (plane_state->base.crtc_h *
> plane_state->base.crtc_w - 1) * fb->format->cpp[0];
> @@ -11356,7 +11356,7 @@ static void intel_dump_pipe_config(struct intel_crtc
> *crtc,
> pipe_config->scaler_state.scaler_users,
> pipe_config->scaler_state.scaler_id);
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds
> border: 0x%08x\n",
> pipe_config->gmch_pfit.control,
> pipe_config->gmch_pfit.pgm_ratios,
> @@ -13096,7 +13096,7 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
>
> /* FIXME unify this for all platforms */
> if (!new_crtc_state->active &&
> - !HAS_GMCH_DISPLAY(dev_priv) &&
> + !HAS_GMCH(dev_priv) &&
> dev_priv->display.initial_watermarks)
>
> dev_priv->display.initial_watermarks(intel_state,
>
> new_intel_crtc_state);
> @@ -15074,7 +15074,7 @@ static void sanitize_watermarks(struct drm_device
> *dev)
> * intermediate watermarks (since we don't trust the current
> * watermarks).
> */
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> intel_state->skip_intermediate_wm = true;
>
> ret = intel_atomic_check(dev, state);
> @@ -15315,7 +15315,7 @@ int intel_modeset_init(struct drm_device *dev)
> * Note that we need to do this after reconstructing the BIOS fb's
> * since the watermark calculation done here will use pstate->fb.
> */
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> sanitize_watermarks(dev);
>
> /*
> @@ -15524,7 +15524,7 @@ static void intel_sanitize_crtc(struct intel_crtc
> *crtc,
> if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
> intel_crtc_disable_noatomic(&crtc->base, ctx);
>
> - if (crtc_state->base.active || HAS_GMCH_DISPLAY(dev_priv)) {
> + if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
> /*
> * We start out with underrun reporting disabled to avoid races.
> * For correct bookkeeping mark this on active crtcs.
> @@ -16271,7 +16271,7 @@ intel_display_capture_error_state(struct
> drm_i915_private *dev_priv)
>
> error->pipe[i].source = I915_READ(PIPESRC(i));
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> error->pipe[i].stat = I915_READ(PIPESTAT(i));
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 681e88405ada..c09c75117e9f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2141,7 +2141,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> return ret;
> }
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> intel_gmch_panel_fitting(intel_crtc, pipe_config,
> conn_state->scaling_mode);
> else
> @@ -2152,7 +2152,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> - if (HAS_GMCH_DISPLAY(dev_priv) &&
> + if (HAS_GMCH(dev_priv) &&
> adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> return -EINVAL;
>
> @@ -5300,7 +5300,7 @@ bool intel_digital_port_connected(struct intel_encoder
> *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (HAS_GMCH_DISPLAY(dev_priv)) {
> + if (HAS_GMCH(dev_priv)) {
> if (IS_GM45(dev_priv))
> return gm45_digital_port_connected(encoder);
> else
> @@ -6038,7 +6038,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> intel_attach_force_audio_property(connector);
>
> intel_attach_broadcast_rgb_property(connector);
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> drm_connector_attach_max_bpc_property(connector, 6, 10);
> else if (INTEL_GEN(dev_priv) >= 5)
> drm_connector_attach_max_bpc_property(connector, 6, 12);
> @@ -6047,7 +6047,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> u32 allowed_scalers;
>
> allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
> BIT(DRM_MODE_SCALE_FULLSCREEN);
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
>
> drm_connector_attach_scaling_mode_property(connector,
> allowed_scalers);
> @@ -6919,7 +6919,7 @@ intel_dp_init_connector(struct intel_digital_port
> *intel_dig_port,
> drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
> drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
>
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> connector->interlace_allowed = true;
> connector->doublescan_allowed = 0;
>
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 3b9285130ef5..f33de4be4b89 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -258,7 +258,7 @@ static bool
> __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
> old = !crtc->cpu_fifo_underrun_disabled;
> crtc->cpu_fifo_underrun_disabled = !enable;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> else if (IS_GEN_RANGE(dev_priv, 5, 6))
> ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
> @@ -369,7 +369,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct
> drm_i915_private *dev_priv,
> return;
>
> /* GMCH can't disable fifo underruns, filter them. */
> - if (HAS_GMCH_DISPLAY(dev_priv) &&
> + if (HAS_GMCH(dev_priv) &&
> crtc->cpu_fifo_underrun_disabled)
> return;
>
> @@ -421,7 +421,7 @@ void intel_check_cpu_fifo_underruns(struct
> drm_i915_private *dev_priv)
> if (crtc->cpu_fifo_underrun_disabled)
> continue;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> i9xx_check_fifo_underruns(crtc);
> else if (IS_GEN(dev_priv, 7))
> ivybridge_check_fifo_underruns(crtc);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 97a98e1bea56..f125a62eba8c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1588,7 +1588,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>
> if (hdmi->has_hdmi_sink && !force_dvi) {
> /* if we can't do 8bpc we may still be able to do 12bpc */
> - if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
> + if (status != MODE_OK && !HAS_GMCH(dev_priv))
> status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
> true, force_dvi);
>
> @@ -1613,7 +1613,7 @@ static bool hdmi_deep_color_possible(const struct
> intel_crtc_state *crtc_state,
> &crtc_state->base.adjusted_mode;
> int i;
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> return false;
>
> if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
> @@ -2150,7 +2150,7 @@ intel_hdmi_add_properties(struct intel_hdmi
> *intel_hdmi, struct drm_connector *c
> drm_connector_attach_content_type_property(connector);
> connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
>
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> drm_connector_attach_max_bpc_property(connector, 8, 12);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
> b/drivers/gpu/drm/i915/intel_hotplug.c
> index e027d2b4abe5..b8937c788f03 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -470,7 +470,7 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> * hotplug bits itself. So only WARN about unexpected
> * interrupts on saner platforms.
> */
> - WARN_ONCE(!HAS_GMCH_DISPLAY(dev_priv),
> + WARN_ONCE(!HAS_GMCH(dev_priv),
> "Received HPD interrupt on pin %d although
> disabled\n", pin);
> continue;
> }
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 4f6dc8c94634..5a733e711355 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -823,7 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> - else if (!HAS_GMCH_DISPLAY(dev_priv))
> + else if (!HAS_GMCH(dev_priv))
> /*
> * Broxton uses the same PCH offsets for South Display Engine,
> * even though it doesn't have a PCH.
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index 696b750acd1d..6403728fe778 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -275,7 +275,7 @@ static int intel_dsi_compute_config(struct intel_encoder
> *encoder,
> if (fixed_mode) {
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>
> - if (HAS_GMCH_DISPLAY(dev_priv))
> + if (HAS_GMCH(dev_priv))
> intel_gmch_panel_fitting(crtc, pipe_config,
> conn_state->scaling_mode);
> else
> @@ -1633,7 +1633,7 @@ static void intel_dsi_add_properties(struct
> intel_connector *connector)
> u32 allowed_scalers;
>
> allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
> BIT(DRM_MODE_SCALE_FULLSCREEN);
> - if (!HAS_GMCH_DISPLAY(dev_priv))
> + if (!HAS_GMCH(dev_priv))
> allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
>
> drm_connector_attach_scaling_mode_property(&connector->base,
> --
> 2.20.1
--
Ville Syrjälä
Intel
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