On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote: > Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the > register isn't there, and use i915_mmio_reg_valid() instead of repeating > the condition all over the place. > > Use INVALID_MMIO_REG explicitly for documentation purposes, even if the > value is unchanged from 0.
great clean up. Thanks for that. Reviewed-by: Rodrigo Vivi <[email protected]> > > Cc: Rodrigo Vivi <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/intel_dp.c | 73 ++++++++++++++++++--------------- > 1 file changed, 39 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index e0f421e76305..f40b3342d82a 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp > *intel_dp, > regs->pp_stat = PP_STATUS(pps_idx); > regs->pp_on = PP_ON_DELAYS(pps_idx); > regs->pp_off = PP_OFF_DELAYS(pps_idx); > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > - !HAS_PCH_ICP(dev_priv)) > + > + /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > + HAS_PCH_ICP(dev_priv)) > + regs->pp_div = INVALID_MMIO_REG; > + else > regs->pp_div = PP_DIVISOR(pps_idx); > } > > @@ -6420,7 +6424,7 @@ static void > intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq > *seq) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; > + u32 pp_on, pp_off, pp_ctl; > struct pps_registers regs; > > intel_pps_get_registers(intel_dp, ®s); > @@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, > struct edp_power_seq *seq) > > pp_on = I915_READ(regs.pp_on); > pp_off = I915_READ(regs.pp_off); > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > - !HAS_PCH_ICP(dev_priv)) { > - pp_div = I915_READ(regs.pp_div); > - } > > /* Pull timing values out of registers */ > seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> > @@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, > struct edp_power_seq *seq) > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > PANEL_POWER_DOWN_DELAY_SHIFT; > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > - HAS_PCH_ICP(dev_priv)) { > + if (i915_mmio_reg_valid(regs.pp_div)) { > + u32 pp_div; > + > + pp_div = I915_READ(regs.pp_div); > + > + seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > + > + } else { > seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; > - } else { > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; > } > } > > @@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct > intel_dp *intel_dp, > bool force_disable_vdd) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - u32 pp_on, pp_off, pp_div, port_sel = 0; > + u32 pp_on, pp_off, port_sel = 0; > int div = dev_priv->rawclk_freq / 1000; > struct pps_registers regs; > enum port port = dp_to_dig_port(intel_dp)->base.port; > @@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct > intel_dp *intel_dp, > (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); > pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); > - /* Compute the divisor for the pp clock, simply match the Bspec > - * formula. */ > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > - HAS_PCH_ICP(dev_priv)) { > - pp_div = I915_READ(regs.pp_ctrl); > - pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > - << BXT_POWER_CYCLE_DELAY_SHIFT); > - } else { > - pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) > - << PANEL_POWER_CYCLE_DELAY_SHIFT); > - } > > /* Haswell doesn't have any port selection bits for the panel > * power sequencer any more. */ > @@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct > intel_dp *intel_dp, > > I915_WRITE(regs.pp_on, pp_on); > I915_WRITE(regs.pp_off, pp_off); > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > - HAS_PCH_ICP(dev_priv)) > - I915_WRITE(regs.pp_ctrl, pp_div); > - else > + > + /* > + * Compute the divisor for the pp clock, simply match the Bspec formula. > + */ > + if (i915_mmio_reg_valid(regs.pp_div)) { > + u32 pp_div; > + > + pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; > + pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) << > + PANEL_POWER_CYCLE_DELAY_SHIFT); > I915_WRITE(regs.pp_div, pp_div); > + } else { > + u32 pp_ctl; > + > + pp_ctl = I915_READ(regs.pp_ctrl); > + pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; > + pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) << > + BXT_POWER_CYCLE_DELAY_SHIFT); > + I915_WRITE(regs.pp_ctrl, pp_ctl); > + } > > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, > PP_OFF %#x, PP_DIV %#x\n", > I915_READ(regs.pp_on), > I915_READ(regs.pp_off), > - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > - HAS_PCH_ICP(dev_priv)) ? > - (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : > - I915_READ(regs.pp_div)); > + i915_mmio_reg_valid(regs.pp_div) ? > + I915_READ(regs.pp_div) : > + (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); > } > > static void intel_dp_pps_init(struct intel_dp *intel_dp) > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
