On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote: > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza > wrote: > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept > > set > > while PSR2 is enabled, it causes some selective updates to fail > > after > > got back from DC6 for the first time. > > So lets clear this register before enabled PSR2, as it could be set > > by a previous i915 module, firmware/BIOS or by a previous mode that > > is not compatible with PSR2. > > Does it happen when you don't have DMC loaded? > > Because It looks like a DMC bug for me... >
BINGO, it do not happens without DMC. > If by removing DMC we don't see the issue, could we please file > this bug to DMC while adding a FIXME with DMC bugged version on it? It happens with GEN9 and GEN10 and reproduced with: icl_dmc_ver1_07.bin and kbl_dmc_ver1_04.bin So updating the comment and commit description to: I will update the comment and commit description to: For some reason if this register is set and when DMC restore the state after a DC6 exit, it causes some PSR2 selective updates to fail, corrupting screen. So for now lets have this workaround until DMC is fixed. > > Aa: Pavana > > If it doesn't happen with DMC loaded than maybe a HSD would for hw > team would be good anyway. I filled a bug in BSpec but in future I will do a HSD instead. > > Cc: Art. > > Thanks, > Rodrigo. > > > Cc: Dhinakaran Pandiyan <[email protected]> > > Cc: Rodrigo Vivi <[email protected]> > > Signed-off-by: José Roberto de Souza <[email protected]> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 7bab6a009e0d..ae62f8124558 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > u32 val; > > + int idle_frames; > > + > > + /* > > + * Keeping this PSR1 register set while PSR2 is enabled causes > > some > > + * PSR2 selective updates to fail, corrupting screen. > > + */ > > + val = I915_READ(EDP_PSR_CTL); > > + if (val & EDP_PSR_TP1_TP3_SEL) > > + I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL); > > > > /* Let's use 6 as the minimum to cover all known cases > > including the > > * off-by-one issue that HW has in some cases. > > */ > > - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); > > - > > + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); > > idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency > > + 1); > > val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; > > > > -- > > 2.21.0 > >
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