The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <[email protected]> --- src/intel_driver.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/intel_driver.h b/src/intel_driver.h index c98025b..0dda5b1 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -219,15 +219,15 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12 -#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 +#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 -- 1.8.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
