On Wed, Mar 20, 2019 at 11:46:35PM +0200, Ville Syrjala wrote: > + /* > + * Try to muzzle SAGV to prevent it from > + * messing up the memory controller readout. > + */ > + intel_disable_sagv(dev_priv); > + > + /* > + * Magic sleep to avoid observing very high DDR clock. > + * Not sure what's going on but on a system with DDR4-3200 > + * clock of 4800 MT/s is often observed here. A short > + * sleep manages to hide that.. Is that actually > + * the "min latency" SAGV point?. Maybe the SA clocks > + * things way up when there is no memory traffic? > + * But polling the register never seems to show this > + * except during i915 unload/load. Sleeping before the > + * SAGV disable usually returns 2133 MT/s. > + * > + * FIXME what is going on? > + */ > + msleep(5);
Argh. Looks like this isn't working on the ci machines. We get <7>[ 12.419386] [drm:i915_driver_load [i915]] SAGV 0 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50 <7>[ 12.419417] [drm:i915_driver_load [i915]] SAGV 1 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50 <7>[ 12.419447] [drm:i915_driver_load [i915]] SAGV 2 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50 Which would indicate 2133 MT/s even though the machines have 3200 MT/s memory (at least according to DMI). -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
