On Fri, 08 Mar 2019, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Allow DP MST to output any color depth. This means deep color as > well as falling back to 6bpc if we would otherwise require too > much bandwidth. > > TODO: We should probably extend bw_contstrained scheme to force > all streams on the link to 6bpc if we can't fit the new stream(s) > otherwise. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_dp.c | 8 +- > drivers/gpu/drm/i915/intel_dp_mst.c | 120 +++++++++++++++++----------- > drivers/gpu/drm/i915/intel_drv.h | 8 ++ > 3 files changed, 83 insertions(+), 53 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index f40b3342d82a..e1ab50980b83 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1724,12 +1724,6 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, > int port_clock, > } > } > > -struct link_config_limits { > - int min_clock, max_clock; > - int min_lane_count, max_lane_count; > - int min_bpp, max_bpp; > -}; > - > static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > const struct intel_crtc_state > *pipe_config) > { > @@ -1792,7 +1786,7 @@ static int intel_dp_compute_bpp(struct intel_dp > *intel_dp, > } > > /* Adjust link config limits based on compliance test requests. */ > -static void > +void > intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config, > struct link_config_limits *limits) > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c > b/drivers/gpu/drm/i915/intel_dp_mst.c > index f9ce9e87d35b..df8b396cbcdc 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -29,41 +29,81 @@ > #include <drm/drm_edid.h> > #include <drm/drm_probe_helper.h> > > +static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state, > + struct drm_connector_state > *conn_state, > + struct link_config_limits *limits) > +{ > + struct drm_atomic_state *state = crtc_state->base.state; > + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); > + struct intel_dp *intel_dp = &intel_mst->primary->dp; > + struct intel_connector *connector = > + to_intel_connector(conn_state->connector); > + const struct drm_display_mode *adjusted_mode = > + &crtc_state->base.adjusted_mode; > + void *port = connector->port; > + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, > + DP_DPCD_QUIRK_CONSTANT_N); > + int slots; > + > + for (;;) {
I'm not particularly fond of having the loop conditions sprinkled in the block. But looks correct. Reviewed-by: Jani Nikula <[email protected]> > + crtc_state->lane_count = limits->max_lane_count; > + crtc_state->port_clock = limits->max_clock; > + crtc_state->pipe_bpp = limits->max_bpp; > + > + crtc_state->pbn = > drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, > + crtc_state->pipe_bpp); > + > + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, > + port, crtc_state->pbn); > + if (slots == -EDEADLK) > + return slots; > + if (slots >= 0) > + break; > + > + if (limits->max_bpp > limits->min_bpp) { > + limits->max_bpp -= 2 * 3; > + continue; > + } > + > + DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots); > + > + return slots; > + } > + > + intel_link_compute_m_n(crtc_state->pipe_bpp, > + crtc_state->lane_count, > + adjusted_mode->crtc_clock, > + crtc_state->port_clock, > + &crtc_state->dp_m_n, > + constant_n); > + crtc_state->dp_m_n.tu = slots; > + > + return 0; > +} > + > static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config, > struct drm_connector_state *conn_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > - struct drm_connector *connector = conn_state->connector; > + struct intel_dp *intel_dp = &intel_mst->primary->dp; > + struct intel_connector *connector = > + to_intel_connector(conn_state->connector); > struct intel_digital_connector_state *intel_conn_state = > to_intel_digital_connector_state(conn_state); > - void *port = to_intel_connector(connector)->port; > - struct drm_atomic_state *state = pipe_config->base.state; > - struct drm_crtc *crtc = pipe_config->base.crtc; > - struct drm_crtc_state *old_crtc_state = > - drm_atomic_get_old_crtc_state(state, crtc); > - int bpp; > - int lane_count, slots = > - to_intel_crtc_state(old_crtc_state)->dp_m_n.tu; > - const struct drm_display_mode *adjusted_mode = > &pipe_config->base.adjusted_mode; > - int mst_pbn; > - bool constant_n = drm_dp_has_quirk(&intel_dp->desc, > - DP_DPCD_QUIRK_CONSTANT_N); > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->base.adjusted_mode; > + void *port = connector->port; > + struct link_config_limits limits; > + int ret; > > if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) > return -EINVAL; > > pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > pipe_config->has_pch_encoder = false; > - bpp = 24; > - if (intel_dp->compliance.test_data.bpc) { > - bpp = intel_dp->compliance.test_data.bpc * 3; > - DRM_DEBUG_KMS("Setting pipe bpp to %d\n", > - bpp); > - } > > if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) > pipe_config->has_audio = > @@ -76,13 +116,21 @@ static int intel_dp_mst_compute_config(struct > intel_encoder *encoder, > * for MST we always configure max link bw - the spec doesn't > * seem to suggest we should do otherwise. > */ > - lane_count = intel_dp_max_lane_count(intel_dp); > + limits.min_clock = > + limits.max_clock = intel_dp_max_link_rate(intel_dp); > + > + limits.min_lane_count = > + limits.max_lane_count = intel_dp_max_lane_count(intel_dp); > > - pipe_config->lane_count = lane_count; > + limits.min_bpp = 6 * 3; > + limits.max_bpp = pipe_config->pipe_bpp; > > - pipe_config->pipe_bpp = bpp; > + intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); > > - pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); > + ret = intel_dp_mst_compute_link_config(encoder, pipe_config, > + conn_state, &limits); > + if (ret) > + return ret; > > if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { > /* > @@ -99,25 +147,6 @@ static int intel_dp_mst_compute_config(struct > intel_encoder *encoder, > intel_conn_state->broadcast_rgb == > INTEL_BROADCAST_RGB_LIMITED; > } > > - mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); > - pipe_config->pbn = mst_pbn; > - > - slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port, > - mst_pbn); > - if (slots < 0) { > - DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", > - slots); > - return slots; > - } > - > - intel_link_compute_m_n(bpp, lane_count, > - adjusted_mode->crtc_clock, > - pipe_config->port_clock, > - &pipe_config->dp_m_n, > - constant_n); > - > - pipe_config->dp_m_n.tu = slots; > - > if (IS_GEN9_LP(dev_priv)) > pipe_config->lane_lat_optim_mask = > > bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); > @@ -401,7 +430,6 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, > struct intel_connector *intel_connector = to_intel_connector(connector); > struct intel_dp *intel_dp = intel_connector->mst_port; > int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; > - int bpp = 24; /* MST uses fixed bpp */ > int max_rate, mode_rate, max_lanes, max_link_clock; > > if (drm_connector_is_unregistered(connector)) > @@ -414,7 +442,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, > max_lanes = intel_dp_max_lane_count(intel_dp); > > max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); > - mode_rate = intel_dp_link_required(mode->clock, bpp); > + mode_rate = intel_dp_link_required(mode->clock, 18); > > /* TODO - validate mode against available PBN for link */ > if (mode->clock < 10000) > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 40ebc94b2187..fe05ed7ff749 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1904,6 +1904,14 @@ void intel_csr_ucode_suspend(struct drm_i915_private > *); > void intel_csr_ucode_resume(struct drm_i915_private *); > > /* intel_dp.c */ > +struct link_config_limits { > + int min_clock, max_clock; > + int min_lane_count, max_lane_count; > + int min_bpp, max_bpp; > +}; > +void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, > + struct intel_crtc_state *pipe_config, > + struct link_config_limits *limits); > bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, > i915_reg_t dp_reg, enum port port, > enum pipe *pipe); -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
