Chris Wilson <[email protected]> writes: > The HW resets it CSB tail pointer on resetting the engine. Most of the > time. In case it doesn't (and for system resume) we write the expected > value anyway. For extra paranoia, flush the write before we invalidate > the cacheline. > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/intel_lrc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 3cb788a223ef..4e0a351bfbca 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1866,6 +1866,7 @@ static void reset_csb_pointers(struct > intel_engine_execlists *execlists) > */ > execlists->csb_head = reset_value; > WRITE_ONCE(*execlists->csb_write, reset_value); > + wmb(); /* Make sure this is visible to HW (paranoia?) */
As alternative tho, how about we invalidate not only the csb portion but the all things included in hswp. Then read the the mmio tail/head, assert they are pointing correctly and match hwsp, if not, correct and log? -Mika > > invalidate_csb_entries(&execlists->csb_status[0], > &execlists->csb_status[reset_value]); > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
