If the engine says it is ready for reset, it is ready so avoid further dancing and proceed.
v2: reg (Chris) Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> --- drivers/gpu/drm/i915/i915_reset.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c index 68875ba43b8d..d874a62103e5 100644 --- a/drivers/gpu/drm/i915/i915_reset.c +++ b/drivers/gpu/drm/i915/i915_reset.c @@ -490,14 +490,20 @@ static int gen11_reset_engines(struct drm_i915_private *i915, static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; + const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); + u32 ctl; int ret; + ctl = intel_uncore_read_fw(uncore, reg); + if (ctl & RESET_CTL_READY_TO_RESET) + return 0; + intel_uncore_write_fw(uncore, - RING_RESET_CTL(engine->mmio_base), + reg, _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); ret = __intel_wait_for_register_fw(uncore, - RING_RESET_CTL(engine->mmio_base), + reg, RESET_CTL_READY_TO_RESET, RESET_CTL_READY_TO_RESET, 700, 0, -- 2.17.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
