On Tue, Jun 18, 2019 at 01:00:00PM -0700, José Roberto de Souza wrote: > The other additional step in the DSI sequqence for EHL. > > BSpec: 20597 > Cc: Uma Shankar <[email protected]> > Cc: Jani Nikula <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index ee85428b309f..3a601c739fc6 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct > intel_encoder *encoder) > I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); > } > } > + > + if (IS_ELKHARTLAKE(dev_priv)) { > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp = I915_READ(ICL_DPHY_CHKN(port)); > + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; > + I915_WRITE(ICL_DPHY_CHKN(port), tmp); > + } > + } > } > > static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1f2c3ebdf87b..dc7b34cf8b42 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1993,6 +1993,10 @@ enum i915_power_well_id { > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > +#define _ICL_DPHY_CHKN_REG 0x194 > +#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + > _ICL_DPHY_CHKN_REG) > +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7) > +
Since this is a new register, should we be using REG_BIT() for the bit definition as described at the top of the file? Other than that, this all matches the bspec so Reviewed-by: Matt Roper <[email protected]> > #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) > > -- > 2.22.0 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
