On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter <dan...@ffwll.ch> wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currently there. > > Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want, > so nothing needs to be changed. Sorry for the confusion.
Shouldn't it be (1<<3) on IVB (for just LLC w/o GFDT), and (3<<3) on the rest? Also what about the GAC_ECO_BITS register? BSpec tells me it exists on IVB and HSW as well. It also seems to have a bit very similar to ECOCHK_SNB_BIT but we don't actually set it on SNB. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
