On Mon, Jul 08, 2019 at 04:16:16PM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulka...@intel.com>
>
> Add a new pll array for Tiger Lake. The TC pll functions for type C will
> be covered in later patches after its phy is implemented.
>
> Cc: Madhav Chauhan <madhav.chau...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 67cfe836286e..ae1c552d7afb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3455,6 +3455,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
> +static const struct dpll_info tgl_plls[] = {
> + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> + /* TODO: Add typeC plls */
> + { },
> +};
> +
> +static const struct intel_dpll_mgr tgl_pll_mgr = {
> + .dpll_info = tgl_plls,
> + .get_dplls = icl_get_dplls,
> + .put_dplls = icl_put_dplls,
> + .dump_hw_state = icl_dump_hw_state,
> +};
> +
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
> @@ -3468,7 +3483,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
> - if (IS_ELKHARTLAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 12)
> + dpll_mgr = &tgl_pll_mgr;
> + else if (IS_ELKHARTLAKE(dev_priv))
> dpll_mgr = &ehl_pll_mgr;
> else if (INTEL_GEN(dev_priv) >= 11)
> dpll_mgr = &icl_pll_mgr;
> --
> 2.21.0
>
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