This patch adds dc3co helper function to enable/disable
psr2 deep sleep.
This patch make sure DC3CO disallowed before PSR2 exit,
it does that essentially by putting a reference to
POWER_DOMAIN_VIDEO before PSR2 exit.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: jose.so...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 69d908e6a050..12765b1f9e33 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR2_CTL, val);
}
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames = 0;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames;
+
+ /*
+ * Let's use 6 as the minimum to cover all known cases including the
+ * off-by-one issue that HW has in some cases.
+ */
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+
+ /* Before PSR2 exit disallow dc3co*/
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+ dev_priv->csr.dc5_wakeref);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private
*dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
--
2.21.0
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