On Tue, Apr 09, 2013 at 01:02:47PM +0300, [email protected] wrote:
> From: Ville Syrjälä <[email protected]>
>
> Increase the number of fence registers to 32 on IVB/HSW. VLV however
> only has 16 fence registers according to the docs.
>
> Increasing the number of fences was attempted before [1], but there was
> some uncertainty about the maximum CPU fence number for FBC. Since then
> BSpec has been updated to state that there are in fact 32 fence registers,
> and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits,
> and the CPU fence number field in the ILK_DPFC_CONTROL register must be
> zero. So now it all makes sense.
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html
>
> v2: Include some background information based on the previous attempt
>
> Signed-off-by: Ville Syrjälä <[email protected]>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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