On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
> reference clock. So let's read out the ref clock before we
> try to compute the bypass clock.
> 
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a93bad0a8..6b75d2a91cd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>       u32 divider;
>       int div;
>  
> +     bxt_de_pll_readout(dev_priv, cdclk_state);
> +
>       if (INTEL_GEN(dev_priv) >= 12)
>               cdclk_state->bypass = cdclk_state->ref / 2;
>       else if (INTEL_GEN(dev_priv) >= 11)
> @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>       else
>               cdclk_state->bypass = cdclk_state->ref;
>  
> -     bxt_de_pll_readout(dev_priv, cdclk_state);
>       if (cdclk_state->vco == 0) {
>               cdclk_state->cdclk = cdclk_state->bypass;
>               goto out;
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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