Added bandwidth calculation algorithm and checks, similar way as it was done for ICL, some constants were corrected according to BSpec.
Signed-off-by: Stanislav Lisovskiy <[email protected]> v2: Start using same icl_get_bw_info function to avoid code duplication. Moved mpagesize to memory info related structure as it is now dependant on memory type. Fixed qi.t_bl field assignment. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600 --- drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 688858ebe4d0..c89fcdccac7e 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -19,6 +19,7 @@ struct intel_qgv_info { u8 num_points; u8 num_channels; u8 t_bl; + u8 mpagesize; enum intel_dram_type dram_type; }; @@ -56,7 +57,13 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, qi->num_channels = (val & 0xf0) >> 4; qi->num_points = (val & 0xf00) >> 8; - qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; + if (IS_GEN(dev_priv, 11)) { + qi->mpagesize = 16; + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; + } else if (IS_GEN(dev_priv, 12)) { + qi->mpagesize = qi->dram_type == INTEL_DRAM_DDR4 ? 16 : 32; + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; + } return 0; } @@ -132,20 +139,26 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) } struct intel_sa_info { - u8 deburst, mpagesize, deprogbwlimit, displayrtids; + u16 displayrtids; + u8 deburst, deprogbwlimit; }; static const struct intel_sa_info icl_sa_info = { .deburst = 8, - .mpagesize = 16, .deprogbwlimit = 25, /* GB/s */ .displayrtids = 128, }; -static int icl_get_bw_info(struct drm_i915_private *dev_priv) +static const struct intel_sa_info tgl_sa_info = { + .deburst = 16, + .deprogbwlimit = 34, /* GB/s */ + .displayrtids = 256, +}; + + +static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; - const struct intel_sa_info *sa = &icl_sa_info; bool is_y_tile = true; /* assume y tile may be used */ int num_channels; int deinterleave; @@ -234,7 +247,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, void intel_bw_init_hw(struct drm_i915_private *dev_priv) { if (IS_GEN(dev_priv, 11)) - icl_get_bw_info(dev_priv); + icl_get_bw_info(dev_priv, &icl_sa_info); + else if (IS_GEN(dev_priv, 12)) + icl_get_bw_info(dev_priv, &tgl_sa_info); } static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, @@ -249,6 +264,10 @@ static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, return min3(icl_max_bw(dev_priv, num_planes, 0), icl_max_bw(dev_priv, num_planes, 1), icl_max_bw(dev_priv, num_planes, 2)); + else if (IS_GEN(dev_priv, 12)) + return min3(icl_max_bw(dev_priv, num_planes, 0), + icl_max_bw(dev_priv, num_planes, 1), + icl_max_bw(dev_priv, num_planes, 2)); else return UINT_MAX; } -- 2.17.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
