From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Sprinkle fall through comments where needed.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
src/intel_module.c | 1 +
src/sna/blt.c | 2 ++
src/sna/gen2_render.c | 21 +++++++++++++++++----
src/sna/gen3_render.c | 24 ++++++++++++++++++------
src/sna/sna_accel.c | 3 +++
src/sna/sna_damage.h | 1 +
src/sna/sna_display.c | 7 ++++---
src/sna/sna_dri2.c | 2 ++
src/sna/sna_driver.c | 1 +
src/sna/sna_render.c | 4 ++--
src/uxa/intel_dri.c | 1 +
11 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/src/intel_module.c b/src/intel_module.c
index a8c9768ee9f8..171b20d83d33 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -692,6 +692,7 @@ static Bool intel_pci_probe(DriverPtr driver,
case PCI_CHIP_I815:
if (!hosted())
break;
+ /* fall through */
default:
return FALSE;
}
diff --git a/src/sna/blt.c b/src/sna/blt.c
index cb90437ad5ad..afc719f6dc8c 100644
--- a/src/sna/blt.c
+++ b/src/sna/blt.c
@@ -1404,6 +1404,7 @@ memcpy_xor(const void *src, void *dst, int bpp,
width /= 2;
or |= or << 8;
}
+ /* fall through */
case 2:
if (width & 1) {
do {
@@ -1421,6 +1422,7 @@ memcpy_xor(const void *src, void *dst, int bpp,
width /= 2;
or |= or << 16;
}
+ /* fall through */
case 4:
w = width;
if (w * 4 == dst_stride && dst_stride == src_stride) {
diff --git a/src/sna/gen2_render.c b/src/sna/gen2_render.c
index e03c44015701..80f684543149 100644
--- a/src/sna/gen2_render.c
+++ b/src/sna/gen2_render.c
@@ -116,10 +116,17 @@ gen2_buf_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
- default: assert(0);
- case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y;
- case I915_TILING_X: v |= BUF_3D_TILED_SURFACE;
- case I915_TILING_NONE: break;
+ default:
+ assert(0);
+ /* fall through */
+ case I915_TILING_Y:
+ v |= BUF_3D_TILE_WALK_Y;
+ /* fall through */
+ case I915_TILING_X:
+ v |= BUF_3D_TILED_SURFACE;
+ /* fall through */
+ case I915_TILING_NONE:
+ break;
}
return v;
}
@@ -131,6 +138,7 @@ gen2_get_dst_format(uint32_t format)
switch (format) {
default:
assert(0);
+ /* fall through */
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
return COLR_BUF_ARGB8888 | BIAS;
@@ -219,10 +227,13 @@ gen2_sampler_tiling_bits(uint32_t tiling)
switch (tiling) {
default:
assert(0);
+ /* fall through */
case I915_TILING_Y:
bits |= TM0S1_TILE_WALK;
+ /* fall through */
case I915_TILING_X:
bits |= TM0S1_TILED_SURFACE;
+ /* fall through */
case I915_TILING_NONE:
break;
}
@@ -277,6 +288,7 @@ gen2_emit_texture(struct sna *sna,
switch (channel->repeat) {
default:
assert(0);
+ /* fall through */
case RepeatNone:
wrap_mode_u = TEXCOORDMODE_CLAMP_BORDER;
break;
@@ -298,6 +310,7 @@ gen2_emit_texture(struct sna *sna,
switch (channel->filter) {
default:
assert(0);
+ /* fall through */
case PictFilterNearest:
filter = (FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
diff --git a/src/sna/gen3_render.c b/src/sna/gen3_render.c
index 166635eba055..e0a7d158015a 100644
--- a/src/sna/gen3_render.c
+++ b/src/sna/gen3_render.c
@@ -131,9 +131,14 @@ static inline uint32_t gen3_buf_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
- case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y;
- case I915_TILING_X: v |= BUF_3D_TILED_SURFACE;
- case I915_TILING_NONE: break;
+ case I915_TILING_Y:
+ v |= BUF_3D_TILE_WALK_Y;
+ /* fall through */
+ case I915_TILING_X:
+ v |= BUF_3D_TILED_SURFACE;
+ /* fall through */
+ case I915_TILING_NONE:
+ break;
}
return v;
}
@@ -400,6 +405,7 @@ static uint32_t gen3_filter(uint32_t filter)
switch (filter) {
default:
assert(0);
+ /* fall through */
case PictFilterNearest:
return (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT |
@@ -1884,9 +1890,14 @@ static uint32_t gen3_ms_tiling(uint32_t tiling)
{
uint32_t v = 0;
switch (tiling) {
- case I915_TILING_Y: v |= MS3_TILE_WALK;
- case I915_TILING_X: v |= MS3_TILED_SURFACE;
- case I915_TILING_NONE: break;
+ case I915_TILING_Y:
+ v |= MS3_TILE_WALK;
+ /* fall through */
+ case I915_TILING_X:
+ v |= MS3_TILED_SURFACE;
+ /* fall through */
+ case I915_TILING_NONE:
+ break;
}
return v;
}
@@ -4981,6 +4992,7 @@ gen3_render_composite_spans(struct sna *sna,
switch (tmp->base.src.u.gen3.type) {
case SHADER_NONE:
assert(0);
+ /* fall through */
case SHADER_ZERO:
if (no_offset) {
tmp->prim_emit =
gen3_emit_composite_spans_primitive_zero_no_offset;
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 934c8f662bea..8266e86d8fea 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -4955,6 +4955,7 @@ try_upload__inplace(PixmapPtr pixmap, RegionRec *region,
case I915_TILING_X:
if (!sna->kgem.memcpy_to_tiled_x)
break;
+ /* fall through */
default:
if (try_upload__tiled_x(pixmap, region, x, y, w, h, bits,
stride))
goto done;
@@ -8719,6 +8720,7 @@ sna_copy_plane_blt(DrawablePtr source, DrawablePtr
drawable, GCPtr gc,
}
default:
assert(0);
+ /* fall through */
case 8:
{
uint8_t *src =
src_pixmap->devPrivate.ptr;
@@ -10123,6 +10125,7 @@ spans_fallback:
switch (gc->lineStyle) {
default:
assert(0);
+ /* fall through */
case LineSolid:
if (gc->lineWidth == 0) {
DBG(("%s: miZeroLine\n", __FUNCTION__));
diff --git a/src/sna/sna_damage.h b/src/sna/sna_damage.h
index d5c727eeee34..abdc786863a9 100644
--- a/src/sna/sna_damage.h
+++ b/src/sna/sna_damage.h
@@ -152,6 +152,7 @@ static inline bool sna_damage_is_all(struct sna_damage
**_damage,
return false;
default:
assert(0);
+ /* fall through */
case DAMAGE_ADD:
if (damage->extents.x2 < width || damage->extents.x1 > 0)
return false;
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index d6210cc7bbc8..1e62cc40473f 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -8309,7 +8309,7 @@ static bool sna_emit_wait_for_scanline_hsw(struct sna
*sna,
sna->kgem.nbatch += 17;
switch (pipe) {
- default: assert(0);
+ default: assert(0); /* fall through */
case 0: event = 1 << 0; break;
case 1: event = 1 << 8; break;
case 2: event = 1 << 14; break;
@@ -8325,7 +8325,7 @@ static bool sna_emit_wait_for_scanline_hsw(struct sna
*sna,
/* The documentation says that the LOAD_SCAN_LINES command
* always comes in pairs. Don't ask me why. */
switch (pipe) {
- default: assert(0);
+ default: assert(0); /* fall through */
case 0: event = 0 << 19; break;
case 1: event = 1 << 19; break;
case 2: event = 4 << 19; break;
@@ -8334,7 +8334,7 @@ static bool sna_emit_wait_for_scanline_hsw(struct sna
*sna,
b[9] = b[7] = (y1 << 16) | (y2-1);
switch (pipe) {
- default: assert(0);
+ default: assert(0); /* fall through */
case 0: event = 1 << 0; break;
case 1: event = 1 << 8; break;
case 2: event = 1 << 14; break;
@@ -8374,6 +8374,7 @@ static bool sna_emit_wait_for_scanline_ivb(struct sna
*sna,
switch (pipe) {
default:
assert(0);
+ /* fall through */
case 0:
event = 1 << (full_height ? 3 : 0);
break;
diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index daa71dc6db30..5fd4d54b6d70 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -680,6 +680,7 @@ sna_dri2_create_buffer(DrawablePtr draw,
(sna->flags & (SNA_LINEAR_FB | SNA_NO_WAIT |
SNA_NO_FLIP)) == 0)
flags |= CREATE_SCANOUT;
}
+ /* fall through */
case DRI2BufferBackRight:
case DRI2BufferFrontRight:
case DRI2BufferFakeFrontLeft:
@@ -2944,6 +2945,7 @@ static void sna_dri2_flip_event(struct sna_dri2_event
*flip)
DBG(("%s: triple buffer swap complete, unblocking
client\n", __FUNCTION__));
frame_swap_complete(flip, DRI2_FLIP_COMPLETE);
}
+ /* fall through */
case FLIP_COMPLETE:
assert(!flip->signal);
if (sna->dri2.flip_pending) {
diff --git a/src/sna/sna_driver.c b/src/sna/sna_driver.c
index 754b2d4f130d..4f8895f1eda2 100644
--- a/src/sna/sna_driver.c
+++ b/src/sna/sna_driver.c
@@ -603,6 +603,7 @@ static Bool sna_pre_init(ScrnInfoPtr scrn, int probe)
if ((sna->flags & SNA_IS_HOSTED) ||
fb_supports_depth(fd, scrn->depth))
break;
+ /* fall through */
default:
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"Given depth (%d) is not supported by the Intel
driver and this chipset.\n",
diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index 1787ffae4874..904d44004d44 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -58,7 +58,7 @@ sna_format_for_depth(int depth)
case 8: return PICT_a8;
case 15: return PICT_x1r5g5b5;
case 16: return PICT_r5g6b5;
- default: assert(0);
+ default: assert(0); /* fall through */
case 24: return PICT_x8r8g8b8;
#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,6,99,900,0)
case 30: return PICT_x2r10g10b10;
@@ -77,7 +77,7 @@ sna_render_format_for_depth(int depth)
case 15: return PIXMAN_a1r5g5b5;
case 16: return PIXMAN_r5g6b5;
case 30: return PIXMAN_a2r10g10b10;
- default: assert(0);
+ default: assert(0); /* fall through */
case 24:
case 32: return PIXMAN_a8r8g8b8;
}
diff --git a/src/uxa/intel_dri.c b/src/uxa/intel_dri.c
index 524826d24082..e707b74f091f 100644
--- a/src/uxa/intel_dri.c
+++ b/src/uxa/intel_dri.c
@@ -302,6 +302,7 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int
attachment,
hint |= INTEL_CREATE_PIXMAP_TILING_Y;
break;
}
+ /* fall through */
case DRI2BufferAccum:
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
--
2.21.0
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