On Wed, Sep 18, 2019 at 05:07:14PM -0700, José Roberto de Souza wrote: > From: Clinton A Taylor <clinton.a.tay...@intel.com> > > Step 4.b was complete missed because it is only required to TC and TBT. > > Bspec: 49190 > Signed-off-by: Clinton A Taylor <clinton.a.tay...@intel.com> > Signed-off-by: José Roberto de Souza <jose.so...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3e6394139964..81792a04e0aa 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3224,11 +3224,14 @@ static void tgl_ddi_pre_enable_dp(struct > intel_encoder *encoder, > intel_edp_panel_on(intel_dp); > > /* > - * 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by: > + * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by: > * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and > * haswell_crtc_enable()->intel_enable_shared_dpll() > */ > > + /* 4.b */ > + intel_ddi_clk_select(encoder, crtc_state);
The BSpec 4.b step could be more specific about the register to program (at least I haven't found the mention about it) but seems to match: Reviewed-by: Imre Deak <imre.d...@intel.com> While reviewing this I noticed that both icl_pll_to_ddi_clk_sel() (missing cases for MGPLL5,6) and intel_phy_is_combo() (not correct for port/phy C) will also need to get updated for TGL. > + > /* 5. */ > if (!intel_phy_is_tc(dev_priv, phy) || > dig_port->tc_mode != TC_PORT_TBT_ALT) > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
