Hi Maarten, I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next] [cannot apply to v5.3 next-20190920] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-i915-dp-Fix-dsc-bpp-calculations-v3/20190923-205540 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-defconfig (attached as .config) compiler: gcc-7 (Debian 7.4.0-13) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <[email protected]> All errors (new ones prefixed by >>): drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config': >> drivers/gpu/drm/i915/display/intel_ddi.c:3905:17: error: implicit >> declaration of function 'TGL_DP_TP_CTL'; did you mean 'DP_TP_CTL'? >> [-Werror=implicit-function-declaration] dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); ^~~~~~~~~~~~~ DP_TP_CTL >> drivers/gpu/drm/i915/display/intel_ddi.c:3905:15: error: incompatible types >> when assigning to type 'i915_reg_t {aka struct <anonymous>}' from type 'int' dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); ^ cc1: some warnings being treated as errors vim +3905 drivers/gpu/drm/i915/display/intel_ddi.c 3826 3827 void intel_ddi_get_config(struct intel_encoder *encoder, 3828 struct intel_crtc_state *pipe_config) 3829 { 3830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3831 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 3832 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3833 u32 temp, flags = 0; 3834 3835 /* XXX: DSI transcoder paranoia */ 3836 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 3837 return; 3838 3839 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3840 if (temp & TRANS_DDI_PHSYNC) 3841 flags |= DRM_MODE_FLAG_PHSYNC; 3842 else 3843 flags |= DRM_MODE_FLAG_NHSYNC; 3844 if (temp & TRANS_DDI_PVSYNC) 3845 flags |= DRM_MODE_FLAG_PVSYNC; 3846 else 3847 flags |= DRM_MODE_FLAG_NVSYNC; 3848 3849 pipe_config->base.adjusted_mode.flags |= flags; 3850 3851 switch (temp & TRANS_DDI_BPC_MASK) { 3852 case TRANS_DDI_BPC_6: 3853 pipe_config->pipe_bpp = 18; 3854 break; 3855 case TRANS_DDI_BPC_8: 3856 pipe_config->pipe_bpp = 24; 3857 break; 3858 case TRANS_DDI_BPC_10: 3859 pipe_config->pipe_bpp = 30; 3860 break; 3861 case TRANS_DDI_BPC_12: 3862 pipe_config->pipe_bpp = 36; 3863 break; 3864 default: 3865 break; 3866 } 3867 3868 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3869 case TRANS_DDI_MODE_SELECT_HDMI: 3870 pipe_config->has_hdmi_sink = true; 3871 3872 pipe_config->infoframes.enable |= 3873 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3874 3875 if (pipe_config->infoframes.enable) 3876 pipe_config->has_infoframe = true; 3877 3878 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3879 pipe_config->hdmi_scrambling = true; 3880 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3881 pipe_config->hdmi_high_tmds_clock_ratio = true; 3882 /* fall through */ 3883 case TRANS_DDI_MODE_SELECT_DVI: 3884 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3885 pipe_config->lane_count = 4; 3886 break; 3887 case TRANS_DDI_MODE_SELECT_FDI: 3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3889 break; 3890 case TRANS_DDI_MODE_SELECT_DP_SST: 3891 if (encoder->type == INTEL_OUTPUT_EDP) 3892 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3893 else 3894 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3895 pipe_config->lane_count = 3896 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3897 intel_dp_get_m_n(intel_crtc, pipe_config); 3898 3899 if (INTEL_GEN(dev_priv) >= 11) { 3900 i915_reg_t dp_tp_ctl; 3901 3902 if (IS_GEN(dev_priv, 11)) 3903 dp_tp_ctl = DP_TP_CTL(pipe_config->cpu_transcoder); 3904 else > 3905 dp_tp_ctl = > TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 3906 3907 pipe_config->fec_enable = 3908 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3909 3910 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 3911 encoder->base.base.id, encoder->base.name, 3912 pipe_config->fec_enable); 3913 } 3914 3915 break; 3916 case TRANS_DDI_MODE_SELECT_DP_MST: 3917 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3918 pipe_config->lane_count = 3919 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3920 intel_dp_get_m_n(intel_crtc, pipe_config); 3921 break; 3922 default: 3923 break; 3924 } 3925 3926 pipe_config->has_audio = 3927 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3928 3929 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3930 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3931 /* 3932 * This is a big fat ugly hack. 3933 * 3934 * Some machines in UEFI boot mode provide us a VBT that has 18 3935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3936 * unknown we fail to light up. Yet the same BIOS boots up with 3937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3938 * max, not what it tells us to use. 3939 * 3940 * Note: This will still be broken if the eDP panel is not lit 3941 * up by the BIOS, and thus we can't get the mode at module 3942 * load. 3943 */ 3944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3945 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3946 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3947 } 3948 3949 intel_ddi_clock_get(encoder, pipe_config); 3950 3951 if (IS_GEN9_LP(dev_priv)) 3952 pipe_config->lane_lat_optim_mask = 3953 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3954 3955 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3956 3957 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3958 3959 intel_read_infoframe(encoder, pipe_config, 3960 HDMI_INFOFRAME_TYPE_AVI, 3961 &pipe_config->infoframes.avi); 3962 intel_read_infoframe(encoder, pipe_config, 3963 HDMI_INFOFRAME_TYPE_SPD, 3964 &pipe_config->infoframes.spd); 3965 intel_read_infoframe(encoder, pipe_config, 3966 HDMI_INFOFRAME_TYPE_VENDOR, 3967 &pipe_config->infoframes.hdmi); 3968 intel_read_infoframe(encoder, pipe_config, 3969 HDMI_INFOFRAME_TYPE_DRM, 3970 &pipe_config->infoframes.drm); 3971 } 3972 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
_______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
