On Thu, Oct 10, 2019 at 12:32:41PM -0700, José Roberto de Souza wrote:
> Those features could be fused off on GEN9 non-low power and newer
> GENs.
Should probably be two patches.
>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39c65f051468..086a8e6e86f1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7643,7 +7643,9 @@ enum {
> #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
Looks correct.
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> +#define SKL_DFSM_DMC_DISABLE (1 << 23)
That seems to be a thing for icl+ only.
> #define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> #define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
> #define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 5cfa197090e2..deeab3790a51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -983,6 +983,12 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> info->display.has_hdcp = 0;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> + info->display.has_fbc = 0;
> +
> + if (!IS_GEN9_BC(dev_priv) && dfsm & SKL_DFSM_DMC_DISABLE)
> + info->display.has_csr = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.23.0
>
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--
Ville Syrjälä
Intel
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