Transcoder timing calculation differ for command mode.
v2: Use is_vid_mode, and use same I915_WRITE (Jani)
Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 39 +++++++++++++++++---------
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 089c630526bc..96f912b153e9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -791,6 +791,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
u16 hback_porch;
/* vertical timings */
u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+ int bpp, line_time_us, byte_clk_period_ns;
hactive = adjusted_mode->crtc_hdisplay;
htotal = adjusted_mode->crtc_htotal;
@@ -828,7 +829,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
}
/* TRANS_HSYNC register to be programmed only for video mode */
- if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+ if (is_vid_mode(intel_dsi)) {
if (intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
/* BSPEC: hsync size should be atleast 16 pixels */
@@ -852,12 +853,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
}
/* program TRANS_VTOTAL register */
+ if (is_cmd_mode(intel_dsi)) {
+ bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ byte_clk_period_ns = 8 * 1000000 / intel_dsi->pclk;
+ htotal = hactive + 160;
+ line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) /
(1000 * intel_dsi->lane_count);
+ vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
+ }
+
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
/*
- * FIXME: Programing this by assuming progressive mode, since
- * non-interlaced info from VBT is not saved inside
- * struct drm_display_mode.
+ * FIXME: Programing this by assuming progressive mode,
+ * since non-interlaced info from VBT is not saved
+ * inside struct drm_display_mode.
* For interlace mode: program required pixel minus 2
*/
I915_WRITE(VTOTAL(dsi_trans),
@@ -870,22 +879,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
if (vsync_start < vactive)
DRM_ERROR("vsync_start less than vactive\n");
- /* program TRANS_VSYNC register */
- for_each_dsi_port(port, intel_dsi->ports) {
- dsi_trans = dsi_port_to_transcoder(port);
- I915_WRITE(VSYNC(dsi_trans),
- (vsync_start - 1) | ((vsync_end - 1) << 16));
+ /* program TRANS_VSYNC register for video mode only */
+ if (is_vid_mode(intel_dsi)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ I915_WRITE(VSYNC(dsi_trans),
+ (vsync_start - 1) | ((vsync_end - 1) << 16));
+ }
}
/*
- * FIXME: It has to be programmed only for interlaced
+ * FIXME: It has to be programmed only for video modes and interlaced
* modes. Put the check condition here once interlaced
* info available as described above.
* program TRANS_VSYNCSHIFT register
*/
- for_each_dsi_port(port, intel_dsi->ports) {
- dsi_trans = dsi_port_to_transcoder(port);
- I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+ if (is_vid_mode(intel_dsi)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+ }
}
/* program TRANS_VBLANK register, should be same as vtotal programmed */
--
2.21.0.5.gaeb582a
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