On Thu, 05 Dec 2019, "Kulkarni, Vandita" <[email protected]> wrote: >> -----Original Message----- >> From: Jani Nikula <[email protected]> >> Sent: Tuesday, November 26, 2019 7:13 PM >> To: [email protected] >> Cc: Nikula, Jani <[email protected]>; Navare, Manasi D >> <[email protected]>; Kulkarni, Vandita >> <[email protected]>; Ville Syrjälä <[email protected]> >> Subject: [PATCH v3 06/13] drm/i915/dsc: add support for computing and >> writing PPS for DSI encoders >> >> Add DSI specific computation and transmission to display of PPS. >> >> With hopes that this approach will work for both DP and DSI encoders. >> >> Cc: Manasi Navare <[email protected]> >> Cc: Vandita Kulkarni <[email protected]> >> Cc: Ville Syrjälä <[email protected]> >> Signed-off-by: Jani Nikula <[email protected]> >> --- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++- >> 1 file changed, 24 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c >> b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index c53024dfb1ec..7bd727129a8f 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -10,6 +10,7 @@ >> >> #include "i915_drv.h" >> #include "intel_display_types.h" >> +#include "intel_dsi.h" >> #include "intel_vdsc.h" >> >> enum ROW_INDEX_BPP { >> @@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct >> intel_encoder *encoder, >> } >> } >> >> +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, >> + const struct intel_crtc_state *crtc_state) { >> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> + struct mipi_dsi_device *dsi; >> + struct drm_dsc_picture_parameter_set pps; >> + enum port port; >> + >> + drm_dsc_pps_payload_pack(&pps, vdsc_cfg); >> + >> + for_each_dsi_port(port, intel_dsi->ports) { >> + dsi = intel_dsi->dsi_hosts[port]->device; >> + >> + mipi_dsi_picture_parameter_set(dsi, &pps); >> + mipi_dsi_compression_mode(dsi, true); >> + } >> +} >> + >> static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state) { >> @@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder >> *encoder, >> > Slightly out of scope of this patch, but I see that while configuring PPS9, > we are using direct macros and not using anything from > vdsc_cfg->rc_model_size and we have not initialized vdsc_cfg-> rc_edge_factor
As mentioned on IRC, we'll need to fix this also for DP I think, and that's indeed slightly out of scope here. BR, Jani. > >> intel_dsc_pps_configure(encoder, crtc_state); >> > Other than that, this patch LGTM. > Reviewed-by: Vandita Kulkarni <[email protected]> > > Thanks, > Vandita >> - intel_dsc_dp_pps_write(encoder, crtc_state); >> + if (encoder->type == INTEL_OUTPUT_DSI) >> + intel_dsc_dsi_pps_write(encoder, crtc_state); >> + else >> + intel_dsc_dp_pps_write(encoder, crtc_state); >> >> if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { >> dss_ctl1_reg = DSS_CTL1; >> -- >> 2.20.1 > -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
