On Tue, Dec 24, 2019 at 03:15:21PM -0800, Matt Roper wrote:
Our usual i915 convention is to assume that future platforms will follow
the same behavior as the latest platform of today. The VDBOX/SFC
capabilities described here don't seem like something that should be
specific to TGL, so let's future-proof by making the test apply to all
gen12+ platforms.
Cc: Lucas De Marchi <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 1acb5db77431..bb709a08bd3c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1093,7 +1093,7 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
* hooked up to an SFC (Scaler & Format Converter) unit.
* In TGL each VDBOX has access to an SFC.
*/
- if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
+ if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)
RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
but why are we even doing this instead of initiliazing them at compile
time on the device_info? If it's fused off, then whatever is set in
vdbox_sfc_access bit shouldn't matter... or if the code making use of
this doesn't check for engine availability, then this part of the
function could just disable the bit of whatever is fused off, regardless
if it's ice lake, tiger lake or whatever.
Lucas De Marchi
}
DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
--
2.23.0
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