From: Ville Syrjälä <[email protected]> Move all the old vs. new state shenanigans into intel_set_cdclk_{pre,post}_plane_update() so that the caller doesn't need to know any of it.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++---------- drivers/gpu/drm/i915/display/intel_cdclk.h | 12 +----- drivers/gpu/drm/i915/display/intel_display.c | 10 +---- 3 files changed, 26 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2a5491eb8af3..a2b1401dcfbb 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1887,41 +1887,41 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, } /** - * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware before updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } /** - * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware after updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 712cdaea4fef..a3fb7b8e8d31 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -33,16 +33,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); -void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); -void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); +void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); +void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index de2ab44b9150..25b0eab019cb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15411,10 +15411,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); - intel_set_cdclk_pre_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_pre_plane_update(state); /* * SKL workaround: bspec recommends we disable the SAGV when we @@ -15450,10 +15447,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { intel_encoders_update_complete(state); - intel_set_cdclk_post_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_post_plane_update(state); } /* FIXME: We should call drm_atomic_helper_commit_hw_done() here -- 2.24.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
