On Thu, Dec 12, 2019 at 02:04:54PM +0000, Chris Wilson wrote: > Execlists uses a scheduling quantum (a timeslice) to alternate execution > between ready-to-run contexts of equal priority. This ensures that all > users (though only if they of equal importance) have the opportunity to > run and prevents livelocks where contexts may have implicit ordering due > to userspace semaphores. > > The timeslicing mechanism can be compiled out with > > ./scripts/config --set-val DRM_I915_TIMESLICE_DURATION 0 > > The timeslice duration can be adjusted per-engine using, > > /sys/class/drm/card?/engine/*/timeslice_duration_ms > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Joonas Lahtinen <[email protected]>
Code looks good. Tested the patch with previous patches in the series. [26/33] drm/i915/gt: Expose engine properties via sysfs [27/33] drm/i915/gt: Expose engine->mmio_base via sysfs The directories and files show up with expected values. Verified that if engine does not have timeslices the sysfs entry is not created. Reviewed-by: Steve Carbonari <[email protected]> Tested-by: Steve Carbonari <[email protected] > --- > drivers/gpu/drm/i915/Kconfig.profile | 3 ++ > drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 46 ++++++++++++++++++++ > 2 files changed, 49 insertions(+) > > diff --git a/drivers/gpu/drm/i915/Kconfig.profile > b/drivers/gpu/drm/i915/Kconfig.profile > index c280b6ae38eb..d8d4a16179bd 100644 > --- a/drivers/gpu/drm/i915/Kconfig.profile > +++ b/drivers/gpu/drm/i915/Kconfig.profile > @@ -73,4 +73,7 @@ config DRM_I915_TIMESLICE_DURATION > is scheduled for execution for the timeslice duration, before > switching to the next context. > > + This is adjustable via > + /sys/class/drm/card?/engine/*/timeslice_duration_ms > + > May be 0 to disable timeslicing. > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c > b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c > index abddd8d0f9ae..b1bd768b13d7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c > @@ -142,6 +142,48 @@ all_caps_show(struct kobject *kobj, struct > kobj_attribute *attr, char *buf) > static struct kobj_attribute all_caps_attr = > __ATTR(known_capabilities, 0444, all_caps_show, NULL); > > +static ssize_t > +timeslice_store(struct kobject *kobj, struct kobj_attribute *attr, > + const char *buf, size_t count) > +{ > + struct intel_engine_cs *engine = kobj_to_engine(kobj); > + unsigned long long duration; > + int err; > + > + /* > + * Execlists uses a scheduling quantum (a timeslice) to alternate > + * execution between ready-to-run contexts of equal priority. This > + * ensures that all users (though only if they of equal importance) > + * have the opportunity to run and prevents livelocks where contexts > + * may have implicit ordering due to userspace semaphores. > + */ > + > + err = kstrtoull(buf, 0, &duration); > + if (err) > + return err; > + > + if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT)) > + return -EINVAL; > + > + WRITE_ONCE(engine->props.timeslice_duration_ms, duration); > + > + if (execlists_active(&engine->execlists)) > + set_timer_ms(&engine->execlists.timer, duration); > + > + return count; > +} > + > +static ssize_t > +timeslice_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) > +{ > + struct intel_engine_cs *engine = kobj_to_engine(kobj); > + > + return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms); > +} > + > +static struct kobj_attribute timeslice_duration_attr = > +__ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store); > + > static void kobj_engine_release(struct kobject *kobj) > { > kfree(kobj); > @@ -206,6 +248,10 @@ void intel_engines_add_sysfs(struct drm_i915_private > *i915) > if (sysfs_create_files(kobj, files)) > goto err_object; > > + if (intel_engine_has_timeslices(engine) && > + sysfs_create_file(kobj, ×lice_duration_attr.attr)) > + goto err_engine; > + > if (0) { > err_object: > kobject_put(kobj); _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
