Now using power_domain mutex to protect from race condition, which can occur because intel_dbuf_slices_update might be running in parallel to gen9_dc_off_power_well_enable being called from intel_dp_detect for instance, which causes assertion triggered by race condition, as gen9_assert_dbuf_enabled might preempt this when registers were already updated, while dev_priv was not.
Signed-off-by: Stanislav Lisovskiy <[email protected]> --- drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 96b38252578b..99ddc21e004c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4404,12 +4404,22 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, { int i; int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + struct i915_power_domains *power_domains = &dev_priv->power_domains; WARN(hweight8(req_slices) > max_slices, "Invalid number of dbuf slices requested\n"); DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices); + /* + * Might be running this in parallel to gen9_dc_off_power_well_enable + * being called from intel_dp_detect for instance, + * which causes assertion triggered by race condition, + * as gen9_assert_dbuf_enabled might preempt this when registers + * were already updated, while dev_priv was not. + */ + mutex_lock(&power_domains->lock); + for (i = 0; i < max_slices; i++) { intel_dbuf_slice_set(dev_priv, _DBUF_CTL_S(i), @@ -4417,6 +4427,8 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, } dev_priv->enabled_dbuf_slices_mask = req_slices; + + mutex_unlock(&power_domains->lock); } static void icl_dbuf_enable(struct drm_i915_private *dev_priv) -- 2.24.1.485.gad05a3d8e5 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
