On Fri, 2020-01-24 at 11:53 -0800, Matt Roper wrote:
> There are reports of unexpected DSB busy/timeout happening after IGT
> tests finish running that apparently go away when the DMC firmware
> isn't
> loaded. The bspec doesn't say anything specific about DSB needing us
> to
> exit DC5/DC6, but let's try adding DSB usage to the "DC off" list and
> see if that changes the behavior.
Makes sense if it fix the issue mentioned
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Cc: Swati Sharma <swati2.sha...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++++---
> drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
> 4 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 761be9fcaf10..99e6afda2db9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -150,6 +150,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "GT_IRQ";
> case POWER_DOMAIN_DPLL_DC_OFF:
> return "DPLL_DC_OFF";
> + case POWER_DOMAIN_DSB:
> + return "DSB";
> default:
> MISSING_CASE(domain);
> return "?";
> @@ -2679,6 +2681,7 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_DSB) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> #define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 2608a65af7fa..5e8136c65e02 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -77,6 +77,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_GT_IRQ,
> POWER_DOMAIN_DPLL_DC_OFF,
> POWER_DOMAIN_INIT,
> + POWER_DOMAIN_DSB,
>
> POWER_DOMAIN_NUM,
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index ada006a690df..156a94a1be05 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -103,7 +103,6 @@ intel_dsb_get(struct intel_crtc *crtc)
> struct drm_i915_gem_object *obj;
> struct i915_vma *vma;
> u32 *buf;
> - intel_wakeref_t wakeref;
>
> if (!HAS_DSB(i915))
> return dsb;
> @@ -111,7 +110,7 @@ intel_dsb_get(struct intel_crtc *crtc)
> if (dsb->refcount++ != 0)
> return dsb;
>
> - wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> + dsb->wakeref = intel_display_power_get(i915, POWER_DOMAIN_DSB);
>
> obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> if (IS_ERR(obj)) {
> @@ -144,7 +143,7 @@ intel_dsb_get(struct intel_crtc *crtc)
> * already be logged above.
> */
>
> - intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> + intel_display_power_put(i915, POWER_DOMAIN_DSB, dsb->wakeref);
>
> return dsb;
> }
> @@ -174,6 +173,8 @@ void intel_dsb_put(struct intel_dsb *dsb)
> dsb->free_pos = 0;
> dsb->ins_start_offset = 0;
> }
> +
> + intel_display_power_put(i915, POWER_DOMAIN_DSB, dsb->wakeref);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 395ef9ce558e..b7ea6e24a78c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -26,6 +26,7 @@ struct intel_dsb {
> enum dsb_id id;
> u32 *cmd_buf;
> struct i915_vma *vma;
> + intel_wakeref_t wakeref;
>
> /*
> * free_pos will point the first free entry position
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