Chris Wilson <[email protected]> writes: > Trust that the HW does the right thing after simply updating the > PD_DIR_BASE?
Bspec offers an invalidate before writing the base. So, lets assume the DCLV write is superfluous as it will be the same. Then the sequence would be TLB_INVLIDATE followed by PP_DIR_BASE (which will all pds) -Mika > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index f915a63e1110..23f4fc2669d1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -1341,14 +1341,10 @@ static int load_pd_dir(struct i915_request *rq, > const struct intel_engine_cs * const engine = rq->engine; > u32 *cs; > > - cs = intel_ring_begin(rq, 12); > + cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); > - *cs++ = valid; > - > *cs++ = MI_LOAD_REGISTER_IMM(1); > *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); > *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; > @@ -1359,10 +1355,6 @@ static int load_pd_dir(struct i915_request *rq, > *cs++ = intel_gt_scratch_offset(engine->gt, > INTEL_GT_SCRATCH_FIELD_DEFAULT); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); > - *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); > - > intel_ring_advance(rq, cs); > > return rq->engine->emit_flush(rq, EMIT_FLUSH); > -- > 2.25.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
