On Wed, 12 Feb 2020, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> We have to write quite a few registers when programming the
> pipe scaler. Let's use intel_de_write_fw() for these to reduce
> the lockdep overhead a bit. All plane registers (including plane
> scaler) already do this.
>
> We already had a few accidental intel_de_write_fw() in there.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++++++------
> 1 file changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 61ba1f2256a0..de50aa0b076c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4494,10 +4494,15 @@ static void skl_detach_scaler(struct intel_crtc
> *intel_crtc, int id)
> {
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Hrmh, I don't like how the uncore lock leaks through the intel_de_*
abstractions. But I guess I dislike adding wrappers for spin locks even
less.
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
>
> - intel_de_write(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
> - intel_de_write(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
> - intel_de_write(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
> + intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> /*
> @@ -6234,6 +6239,7 @@ static void skl_pfit_enable(const struct
> intel_crtc_state *crtc_state)
> if (crtc_state->pch_pfit.enabled) {
> u16 uv_rgb_hphase, uv_rgb_vphase;
> int pfit_w, pfit_h, hscale, vscale;
> + unsigned long irqflags;
> int id;
>
> if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> @@ -6249,16 +6255,21 @@ static void skl_pfit_enable(const struct
> intel_crtc_state *crtc_state)
> uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
>
> id = scaler_state->scaler_id;
> - intel_de_write(dev_priv, SKL_PS_CTRL(pipe, id),
> - PS_SCALER_EN | PS_FILTER_MEDIUM |
> scaler_state->scalers[id].mode);
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN
> |
> + PS_FILTER_MEDIUM |
> scaler_state->scalers[id].mode);
> intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> PS_Y_PHASE(0) |
> PS_UV_RGB_PHASE(uv_rgb_vphase));
> intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> PS_Y_PHASE(0) |
> PS_UV_RGB_PHASE(uv_rgb_hphase));
> - intel_de_write(dev_priv, SKL_PS_WIN_POS(pipe, id),
> - crtc_state->pch_pfit.pos);
> - intel_de_write(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> - crtc_state->pch_pfit.size);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> + crtc_state->pch_pfit.pos);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> + crtc_state->pch_pfit.size);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> }
--
Jani Nikula, Intel Open Source Graphics Center
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