From: Ville Syrjälä <[email protected]> Add the names of all VLV DPIO registers.
Implement a quick and hacky solution to make the tool "detect" DPIO registers by checking if the file name contains the string "dpio". Signed-off-by: Ville Syrjälä <[email protected]> --- tools/quick_dump/Makefile.am | 2 +- tools/quick_dump/quick_dump.py | 13 +++++++---- tools/quick_dump/valleyview | 1 + tools/quick_dump/vlv_dpio.txt | 53 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 tools/quick_dump/vlv_dpio.txt diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index afd6814..cc19987 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -25,7 +25,7 @@ EXTRA_DIST = \ base_display.txt base_interrupt.txt base_other.txt base_power.txt base_rings.txt \ gen6_other.txt sandybridge \ gen7_other.txt ivybridge \ - vlv_display.txt valleyview \ + vlv_display.txt vlv_dpio.txt valleyview \ quick_dump.py \ reg_access.py \ chipset.i chipset.py diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py index 6111b5d..2631b03 100755 --- a/tools/quick_dump/quick_dump.py +++ b/tools/quick_dump/quick_dump.py @@ -8,12 +8,15 @@ import subprocess import chipset import reg_access as reg -def parse_file(file): +def parse_file(file, is_dpio): print('{0:^10s} | {1:^28s} | {2:^10s}'. format('offset', file.name, 'value')) print('-' * 54) for line in file: register = ast.literal_eval(line) - val = reg.read(register[1]) + if is_dpio: + val = reg.dpio_read(register[1]) + else: + val = reg.read(register[1]) intreg = int(register[1], 16) print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val)) print('') @@ -38,7 +41,8 @@ if args.baseless == False: for name in files: if name.startswith(("base_")): file = open(name.rstrip(), 'r') - parse_file(file) + is_dpio = 'dpio' in name.lower() + parse_file(file, is_dpio) if args.autodetect: pci_dev = chipset.intel_get_pci_device() @@ -59,4 +63,5 @@ if args.profile == None: for extra in args.profile: extra_file = open(extra.rstrip(), 'r') - parse_file(extra_file) + is_dpio = 'dpio' in extra.lower() + parse_file(extra_file, is_dpio) diff --git a/tools/quick_dump/valleyview b/tools/quick_dump/valleyview index 4d7dee1..6b6e16c 100644 --- a/tools/quick_dump/valleyview +++ b/tools/quick_dump/valleyview @@ -5,3 +5,4 @@ base_other.txt base_power.txt base_rings.txt gen7_other.txt +vlv_dpio.txt diff --git a/tools/quick_dump/vlv_dpio.txt b/tools/quick_dump/vlv_dpio.txt new file mode 100644 index 0000000..07c713c --- /dev/null +++ b/tools/quick_dump/vlv_dpio.txt @@ -0,0 +1,53 @@ +('DPIO_TX3_SWING_CTL4_A', '0x690', '') +('DPIO_TX3_SWING_CTL4_B', '0x2a90', '') +('DPIO_DIV_A', '0x800c', '') +('DPIO_DIV_B', '0x802c', '') +('DPIO_REFSFR_A', '0x8014', '') +('DPIO_REFSFR_B', '0x8034', '') +('DPIO_CORE_CLK_A', '0x801c', '') +('DPIO_CORE_CLK_B', '0x803c', '') +('DPIO_IREF_CTL_A', '0x8040', '') +('DPIO_IREF_CTL_B', '0x8060', '') +('DPIO_IREF_BCAST', '0xc044', '') +('DPIO_IREF_A', '0x8044', '') +('DPIO_IREF_B', '0x8064', '') +('DPIO_PLL_CML_A', '0x804c', '') +('DPIO_PLL_CML_B', '0x806c', '') +('DPIO_LPF_COEFF_A', '0x8048', '') +('DPIO_LPF_COEFF_B', '0x8068', '') +('DPIO_CALIBRATION', '0x80ac', '') +('DPIO_FASTCLK_DISABLE', '0x8100', '') +('DPIO_PCS_TX_0', '0x8200', '') +('DPIO_PCS_TX_1', '0x8400', '') +('DPIO_PCS_CLK_0', '0x8204', '') +('DPIO_PCS_CLK_1', '0x8404', '') +('DPIO_PCS_CTL_OVR1_A', '0x8224', '') +('DPIO_PCS_CTL_OVR1_B', '0x8424', '') +('DPIO_PCS_STAGGER0_A', '0x822c', '') +('DPIO_PCS_STAGGER0_B', '0x842c', '') +('DPIO_PCS_STAGGER1_A', '0x8230', '') +('DPIO_PCS_STAGGER1_B', '0x8430', '') +('DPIO_PCS_CLOCKBUF0_A', '0x8238', '') +('DPIO_PCS_CLOCKBUF0_B', '0x8438', '') +('DPIO_PCS_CLOCKBUF8_A', '0x825c', '') +('DPIO_PCS_CLOCKBUF8_B', '0x845c', '') +('DPIO_TX_SWING_CTL2_A', '0x8288', '') +('DPIO_TX_SWING_CTL2_B', '0x8488', '') +('DPIO_TX_SWING_CTL3_A', '0x828c', '') +('DPIO_TX_SWING_CTL3_B', '0x848c', '') +('DPIO_TX_SWING_CTL4_A', '0x8290', '') +('DPIO_TX_SWING_CTL4_B', '0x8490', '') +('DPIO_TX_OCALINIT_0', '0x8294', '') +('DPIO_TX_OCALINIT_1', '0x8494', '') +('DPIO_TX_CTL_0', '0x82ac', '') +('DPIO_TX_CTL_1', '0x84ac', '') +('DPIO_TX_LANE_0', '0x82b8', '') +('DPIO_TX_LANE_1', '0x84b8', '') +('DPIO_DATA_CHANNEL1', '0x8220', '') +('DPIO_DATA_CHANNEL2', '0x8420', '') +('DPIO_PORT0_PCS0', '0x0220', '') +('DPIO_PORT0_PCS1', '0x0420', '') +('DPIO_PORT1_PCS2', '0x2620', '') +('DPIO_PORT1_PCS3', '0x2820', '') +('DPIO_DATA_CHANNEL1', '0x8220', '') +('DPIO_DATA_CHANNEL2', '0x8420', '') -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
